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| author | Roy Mingi Park <roy.mingi.park@intel.com> | 2019-04-13 15:16:50 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-04-22 18:00:13 +0000 |
| commit | e3f5f2155a75687ab50d53c49977748f4cecdb2b (patch) | |
| tree | fa5685287348d53950039350033a045c37ea7811 /src/soc/intel/braswell/tsc_freq.c | |
| parent | c94ba798d6f3aa3bf49f6d00d7bb18a4cc00268f (diff) | |
mb/google/sarien: Configure both GPP_H12 and GPP_H13 for SSD on Arcada
Currently, Arcada only supports D3hot during S0iX and there is leakage
power around 5~10mW depending on SSD vendors.
To support D3cold for SSD during S0iX, one MOSFET will be added on DVT2
and two GPIOs are required to be configured.
GPP_H13 is to control SSD_SCP_PWR_EN(power enable) and GPP_H12 is to
control SSD reset.
BUG=b:130741066
TEST=Measure SSD power during S0iX from Arcada(DVT2)
Change-Id: I868590e9e85d5df07930a3681884e3fc3a5c4d50
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32361
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/tsc_freq.c')
0 files changed, 0 insertions, 0 deletions