diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-04-20 15:20:28 -0700 |
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committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-06-25 21:50:48 +0200 |
commit | 32471729d9ebbabe809711ec55568925c6ce2070 (patch) | |
tree | b9f6db4e4969ee5edd6c2571e4f7612121070a9f /src/soc/intel/braswell/stage_cache.c | |
parent | 5fe62efb77a2ecfeecdcc526404712b816e74693 (diff) |
Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC.
BRANCH=none
BUG=None
TEST=Build for a Braswell platform
Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/stage_cache.c')
-rw-r--r-- | src/soc/intel/braswell/stage_cache.c | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/src/soc/intel/braswell/stage_cache.c b/src/soc/intel/braswell/stage_cache.c deleted file mode 100644 index 47d756c7b7..0000000000 --- a/src/soc/intel/braswell/stage_cache.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include <soc/smm.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - char *smm_base; - /* 1MiB cache size */ - const long cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* Ramstage cache lives in TSEG region which is the definition of - * cbmem_top(). */ - smm_base = cbmem_top(); - *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; -} |