soc/intel/cmn/cse: Refactor CSE RW FW Version implementation

This patch introduces a CSE firmware specific data in order
to store Intel CSE and associated firmware related information which
requires a sync between Pre-RAM and Post-RAM phase.

This information will be used further to retrieve currently running
CSE RW firmware instead of fetching the version information by sending
a HECI cmd (which consumes 7ms-15ms depending upon the CSE operational
state).

Current implementation attempts to simply the CSE RW FW version store
and retrieval operations as below

* CSE sync in romstage (aka Pre-RAM) - Relying on .bss segment to store
  the CSE info data in absence of real physical memory and sync back into
  the CBMEM once available (after FSP-M exits).

* CSE sync in ramstage (aka Post-RAM) - Directly stored the CSE RW
  version into the CBMEM (as CBMEM is online).

BUG=b:285405031
TEST=Able to build and boot google/rex. Verified CSE RW FW version
(for LITE SKU) is getting displayed without impacting the boot time.

w/o this patch:
  10:start of ramstage                         722,257 (43)
  17:starting LZ4 decompress (ignore for x86)  723,777 (1,520)

w/ this patch:
  10:start of ramstage                         722,257 (43)
  17:starting LZ4 decompress (ignore for x86)  723,777 (1,520)

Change-Id: Ia873af512851a682cf1fac0e128d842562a316ab
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77174
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

0 files changed, 0 insertions, 0 deletions