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| author | John Su <john_su@compal.corp-partner.google.com> | 2023-05-19 09:57:48 +0800 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-05-23 02:03:52 +0000 |
| commit | a398b311084c60b3ed31fdda93217780bc38a497 (patch) | |
| tree | b071e2d8ce3e8d4344b78c09fd0ffd74369508dc /src/soc/intel/braswell/pcie.c | |
| parent | d6b4db159b60089c3d6e9aad993804ea319047e2 (diff) | |
mb/google/skyrim/var/markarth: Update DPTC and STT settings
According to Thermal table 0518, adjust DPTC and STT settings.
BRANCH=none
BUG=b:273636128
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Id1c1884eabc1ea58148270f39eaca836ccc3fb54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/braswell/pcie.c')
0 files changed, 0 insertions, 0 deletions