summaryrefslogtreecommitdiff
path: root/src/soc/intel/braswell/lpss.c
diff options
context:
space:
mode:
authorBen Gardner <gardner.ben@gmail.com>2015-12-07 11:33:45 -0600
committerPatrick Georgi <pgeorgi@google.com>2015-12-10 08:25:47 +0100
commitfad23134009291a7b992c1323ca815421a4b557d (patch)
treef4595f5ef9dc3aadea9c9e788e9772233cf771ef /src/soc/intel/braswell/lpss.c
parent7e7a4df58075fdff4293d2203b035b970d21aeb8 (diff)
intel/fsp_baytrail: Remove code for nonexistant BBAR
The BBAR register (BIOS Base Address Configuration Register) defined in the ICH9 datasheet does not exist in the Bay Trail E3800 datasheet. Accessing it seems harmless, but should likely be avoided. Change-Id: I5d9a6a1ccead84c8996796f516a2bdc5f248cfef Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12671 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell/lpss.c')
0 files changed, 0 insertions, 0 deletions