diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 10:28:20 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 16:37:13 +0000 |
| commit | 066e61f3ea1f65012b14467412e6b17351c87dc6 (patch) | |
| tree | 0536c4c8d9059f1b765cc2388f6d6974d0486d54 /src/soc/intel/braswell/lpe.c | |
| parent | ad87d1c8b9285cfed47b3ec060be520a467189ff (diff) | |
soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND register
Change-Id: Ie213b8c08e2d2b33a1dc1fda632163160d1cd70e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell/lpe.c')
| -rw-r--r-- | src/soc/intel/braswell/lpe.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 9c4d2b1819..363b57ffa5 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -45,7 +45,7 @@ static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ |