From 066e61f3ea1f65012b14467412e6b17351c87dc6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 10:28:20 +0200 Subject: soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND register Change-Id: Ie213b8c08e2d2b33a1dc1fda632163160d1cd70e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40849 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/braswell/lpe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/braswell/lpe.c') diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 9c4d2b1819..363b57ffa5 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -45,7 +45,7 @@ static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ -- cgit v1.2.3