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author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-16 21:29:33 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-19 13:13:46 +0000 |
commit | a880720ee1820dcb3370cc0d19bf9004faaed9ee (patch) | |
tree | 39757d19a73f0ed93ae7f11b9a0c7706b872dee9 /src/soc/intel/braswell/include | |
parent | ce8dfc51ecccacc285e83d102679583c6094b42e (diff) |
nb/amd/pi/00730F01/northbridge: rework hw_mem_hole_info
This APU is always a single-node and also only has one DRAM controller,
so we don't need to loop over the different nodes to find the memory
hole below 4GB. We also don't need to check for the special case where
the memory hole is non-DRAM address space between the parts of the
address space decoded by different DRAM controllers.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9793d911d2d496be49168c06d83ceb802bc2b647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/braswell/include')
0 files changed, 0 insertions, 0 deletions