intel/braswell: Remove duplicate set_max_freq() prototypes

Change-Id: I13ec9f477c64831848fb0e80b97bfbc10896c195
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>

4 files changed, 1 insertions, 24 deletions

diff --git a/src/soc/intel/braswell/include/soc/bootblock.h b/src/soc/intel/braswell/include/soc/bootblock.h
deleted file mode 100644
index e6e25ccbb1..0000000000
--- a/src/soc/intel/braswell/include/soc/bootblock.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_BOOTBLOCK_H_
-#define _SOC_BOOTBLOCK_H_
-
-void set_max_freq(void);
-
-#endif /* _SOC_BOOTBLOCK_H_ */
diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h
index 6137820e9f..d0bfc8ad4a 100644
--- a/src/soc/intel/braswell/include/soc/msr.h
+++ b/src/soc/intel/braswell/include/soc/msr.h
@@ -41,5 +41,6 @@
 
 /* Read BCLK from MSR */
 unsigned int cpu_bus_freq_khz(void);
+void set_max_freq(void);
 
 #endif /* _SOC_MSR_H_ */
diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h
index f197bc8e1f..17db2d8f75 100644
--- a/src/soc/intel/braswell/include/soc/ramstage.h
+++ b/src/soc/intel/braswell/include/soc/ramstage.h
@@ -98,7 +98,6 @@ enum {
  */
 void soc_init_pre_device(struct soc_intel_braswell_config *config);
 void soc_init_cpus(struct device *dev);
-void set_max_freq(void);
 void southcluster_enable_dev(struct device *dev);
 void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
 int SocStepping(void);
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 9fad9bc5a0..c9b559ac35 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -24,7 +24,6 @@
 
 void gfx_init(void);
 void punit_init(void);
-void set_max_freq(void);
 
 /* romstage.c functions */
 int chipset_prev_sleep_state(struct chipset_power_state *ps);