diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-01-09 16:17:45 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-01-10 17:49:19 +0000 |
| commit | 85144d9002d6a712ce793b87e739f613080fcc4a (patch) | |
| tree | 82082476922ab16e0b5d99e1f9ea54146fa2fb0a /src/soc/intel/braswell/fadt.c | |
| parent | 9a1b720b1f9ea5e589c3e93d16e9a161683f2a4d (diff) | |
soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs
List of changes:
1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per
EDS.
2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
3. Rename PcieRpEnable to PchPcieRpEnable.
4. Enable CPU RPs as below in mainboard devicetree.cb
RP1: PEG60 : 0:6:0 : CPU SSD1
RP2: PEG10 : 0:1:0 : x8 CPU Slot
RP3: PEG62 : 0:6:2 : CPU SSD2
Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/fadt.c')
0 files changed, 0 insertions, 0 deletions