diff options
| author | John Zhao <john.zhao@intel.com> | 2021-01-28 10:57:53 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-04 09:53:15 +0000 |
| commit | 21e2b5a0ce790b1f67c13a140b28635b3acf4a08 (patch) | |
| tree | 39acabafa85f7f84d9f90375bacc9be54f820ec9 /src/soc/intel/braswell/elog.c | |
| parent | cfa02256a5098e8449b4cbc1830990fac75d5fc1 (diff) | |
soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0
A minimum of 100ms delay is required before sending a configuration
request to the downstream components. Since the kernel already adds
100ms, this change drops the extra 100ms delay in TBT PCIe root ports
_PS0 method in order to improve resume time.
BUG=b:177519081
TEST=Boot to kernel and validated various tests on Voxel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/elog.c')
0 files changed, 0 insertions, 0 deletions