diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-04-20 15:20:28 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-06-25 21:50:48 +0200 |
| commit | 32471729d9ebbabe809711ec55568925c6ce2070 (patch) | |
| tree | b9f6db4e4969ee5edd6c2571e4f7612121070a9f /src/soc/intel/braswell/acpi/gpio.asl | |
| parent | 5fe62efb77a2ecfeecdcc526404712b816e74693 (diff) | |
Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC.
BRANCH=none
BUG=None
TEST=Build for a Braswell platform
Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/acpi/gpio.asl')
| -rw-r--r-- | src/soc/intel/braswell/acpi/gpio.asl | 69 |
1 files changed, 49 insertions, 20 deletions
diff --git a/src/soc/intel/braswell/acpi/gpio.asl b/src/soc/intel/braswell/acpi/gpio.asl index abe58901ca..4f1114f60e 100644 --- a/src/soc/intel/braswell/acpi/gpio.asl +++ b/src/soc/intel/braswell/acpi/gpio.asl @@ -21,26 +21,26 @@ #include <soc/iomap.h> #include <soc/irq.h> -/* SouthCluster GPIO */ -Device (GPSC) +/* GPIO SouthWest Community */ +Device (GPSW) { - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") Name (_UID, 1) Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) { - GPIO_SC_IRQ + GPIO_SW_IRQ } }) Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHWEST, RBAS) Return (^RBUF) } @@ -50,26 +50,26 @@ Device (GPSC) } } -/* NorthCluster GPIO */ +/* GPIO North Community */ Device (GPNC) { - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") Name (_UID, 2) Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) { - GPIO_NC_IRQ + GPIO_N_IRQ } }) Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPNORTH, RBAS) Return (^RBUF) } @@ -79,26 +79,55 @@ Device (GPNC) } } -/* SUS GPIO */ -Device (GPSS) +/* GPIO East Community */ +Device (GPEC) { - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") Name (_UID, 3) Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) { - GPIO_SUS_IRQ + GPIO_E_IRQ } }) Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPEAST, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + Return (0xF) + } +} + +/* GPIO SouthEast Community */ +Device (GPSE) +{ + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") + Name (_UID, 4) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) + { + GPIO_SE_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHEAST, RBAS) Return (^RBUF) } |