diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-08-25 18:03:31 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-09 20:18:23 +0000 |
| commit | 3bad4cb086276a0fef715a3e661b489c59e27e08 (patch) | |
| tree | 4b8c9e2976c550439549d200d86187ad4d446035 /src/soc/intel/braswell/acpi/cpu.asl | |
| parent | f966d3b3ae7c52691cfc5697c784c7e99f7d2fff (diff) | |
braswell: acpi: Allow DPTF thresholds to be defined at board-level
Similar to Skylake, allow braswell mainboards to override the default
DPTF thresholds.
BUG=chrome-os-partner:43884
TEST=Build for Strago
BRANCH=Strago
Change-Id: Id2574e98c444b8bf4da8ca36f3eeeb06568e78e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 799a7006e8fcacfea8e8e0de5c99c3ce3c4ac34f
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: If69627163237674a28fb8a26b4ce1886e5dbfc17
Original-Reviewed-on: https://chromium-review.googlesource.com/296033
Original-Commit-Ready: Shawn N <shawnn@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11546
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/acpi/cpu.asl')
| -rw-r--r-- | src/soc/intel/braswell/acpi/cpu.asl | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl index 0ae51f2002..c9cb83b915 100644 --- a/src/soc/intel/braswell/acpi/cpu.asl +++ b/src/soc/intel/braswell/acpi/cpu.asl @@ -18,17 +18,6 @@ * Foundation, Inc. */ -/* CPU */ -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 90 -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 90 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 80 -#define DPTF_CPU_ACTIVE_AC2 70 -#define DPTF_CPU_ACTIVE_AC3 60 -#define DPTF_CPU_ACTIVE_AC4 50 - /* These devices are created at runtime */ External (\_PR.CP00, DeviceObj) External (\_PR.CP01, DeviceObj) |