diff options
| author | shkim <sh_.kim@samsung.com> | 2015-09-22 17:53:58 +0900 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-28 20:46:23 +0100 |
| commit | cc728f02846a1752215503dc7897caf6fc5a1fc1 (patch) | |
| tree | 807c58c07a79e8e0d98777dc72e27f78efac92f1 /src/soc/intel/braswell/Makefile.inc | |
| parent | e8cc52fab012798dd9f5ad12cd6a8d238ea360c7 (diff) | |
soc/braswell: Add interface to program USB2_COMPBG register
Add interface to program USB2_COMPBG register to set
HS_DISC_BG and HS_SQ reference voltage for each project.
TEST=Get build success and do EFT test
Original-Reviewed-on: https://chromium-review.googlesource.com/300846
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Tested-by: shkim <sh_.kim@samsung.com>
Change-Id: If2201829e1a16b4f9916547f08c24e9291358325
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Signed-off-by: shkim <sh_.kim@samsung.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12739
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/braswell/Makefile.inc')
| -rw-r--r-- | src/soc/intel/braswell/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 4a107ec48c..867ce43f16 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += southcluster.c ramstage-y += spi.c ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c ramstage-y += tsc_freq.c +ramstage-y += xhci.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c |