From cc728f02846a1752215503dc7897caf6fc5a1fc1 Mon Sep 17 00:00:00 2001 From: shkim Date: Tue, 22 Sep 2015 17:53:58 +0900 Subject: soc/braswell: Add interface to program USB2_COMPBG register Add interface to program USB2_COMPBG register to set HS_DISC_BG and HS_SQ reference voltage for each project. TEST=Get build success and do EFT test Original-Reviewed-on: https://chromium-review.googlesource.com/300846 Original-Reviewed-by: Shawn N Original-Tested-by: shkim Change-Id: If2201829e1a16b4f9916547f08c24e9291358325 Signed-off-by: Kenji Chen Signed-off-by: shkim Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/12739 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/braswell/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/braswell/Makefile.inc') diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 4a107ec48c..867ce43f16 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += southcluster.c ramstage-y += spi.c ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c ramstage-y += tsc_freq.c +ramstage-y += xhci.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c -- cgit v1.2.3