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authorFurquan Shaikh <furquan@chromium.org>2016-10-18 14:25:25 -0700
committerFurquan Shaikh <furquan@google.com>2016-10-26 08:33:37 +0200
commit3bfe3404df32ca226c624be0435c640bf1ebeae7 (patch)
tree0eef45f9ad972dec851f902d84470cb0b54c3cbf /src/soc/intel/braswell/Kconfig
parentffb3a2d22506a86e205a757029f60abccfef0486 (diff)
intel/skylake: Add support to enable wake-on-usb attach/detach
Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register. Only part missing was #3. This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports. BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach. Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17056 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/Kconfig')
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