diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-24 13:43:39 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-04 15:43:30 +0000 |
| commit | 79ccc6933284ca02d17d9e1eda9a531ce43e1f65 (patch) | |
| tree | 49fe1b78916338575b1a6bec931e2fb885cc311a /src/soc/intel/baytrail | |
| parent | f3161df2eba8d61445372a9c732c61a1947064bd (diff) | |
src: capitalize 'PCIe'
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/baytrail')
| -rw-r--r-- | src/soc/intel/baytrail/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/include/soc/nvs.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/pcie.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 703e20fa8a..a8b0f53719 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -99,7 +99,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 4a89eb967e..8532728503 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -83,7 +83,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 6dc0346b23..6b6c28d731 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -163,7 +163,7 @@ static u8 all_ports_no_dev_present(struct device *dev) dev->path.pci.devfn &= ~0x7; dev->path.pci.devfn |= func; - /* is pcie device there */ + /* is PCIe device there */ if (pci_read_config32(dev, 0) == 0xFFFFFFFF) continue; |