diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-03-16 19:02:26 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-14 19:45:56 +0000 |
| commit | 4bd9187dadaf4f3be5a1776d98d1f79cdfb23de8 (patch) | |
| tree | cadad49316ba0b6e77d9304a5505dcede8860ea5 /src/soc/intel/baytrail | |
| parent | 3dc1792f1df9a9cd982bb63d3b29cc16c08bd7f6 (diff) | |
ACPI: Refactor use of global and device NVS
After ChromeOS NVS was moved to a separate allocation and the use
of multiple OperationRegions, maintaining the fixed offsets is not
necessary.
Use actual structure size for OperationRegions, but align the
allocations to 8 bytes or sizeof(uint64_t).
Change-Id: I9c73b7c44d234af42c571b23187b924ca2c3894a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail')
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/ramstage.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/smihandler.c | 4 |
3 files changed, 7 insertions, 4 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index a9ba092279..9af65ee062 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -8,7 +8,6 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ACPI_HAS_DEVICE_NVS select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 0b681b0212..26e0b6e46d 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -13,6 +13,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> +#include <soc/device_nvs.h> #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/msr.h> @@ -116,6 +117,11 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } +size_t size_of_dnvs(void) +{ + return sizeof(struct device_nvs); +} + /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps) { diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index e48ddbacab..20e15902b1 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -20,8 +20,6 @@ #include <soc/nvs.h> #include <soc/device_nvs.h> -#include <vendorcode/google/chromeos/gnvs.h> - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -210,7 +208,7 @@ static void southbridge_smi_gsmi(void) void *acpi_get_device_nvs(void) { - return (u8 *)gnvs + GNVS_DEVICE_NVS_OFFSET; + return (u8 *)gnvs + ALIGN_UP(sizeof(struct global_nvs), sizeof(uint64_t)); } /* |