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authorJulius Werner <jwerner@chromium.org>2014-12-09 12:18:00 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-20 10:19:56 +0200
commitcdf92eacd5d2f85de473778cc1ebf35c2468a7f2 (patch)
tree6123dc35c53e3122b7433730b18f4169d02535c2 /src/soc/intel/baytrail/southcluster.c
parent0b29a7b37c19200516dadc5c4bf0a1eb9d1290ec (diff)
rk3288: Disable ramstage compression by default
The ramstage is loaded from romstage, so the LZMA scratchpad buffer used to decompress it is part of the romstage BSS in SRAM. On RK3288, SRAM cannot be cached which makes the decompression so slow that it's faster to just load an uncompressed image from SPI. Disable ramstage compression on this SoC to account for that. [pg: implementation avoids restructuring all of Kconfig] BRANCH=None BUG=None TEST=Built for Pinky and Falco, confirmed that the former didn't have COMPRESS_RAMSTAGE in its .config and the latter still did. Measured a speed-up of about 35ms on Pinky. (For some weird reason, the decompression of the payload also takes way longer than on other platforms, although not as long as the ramstage. I have no explanation for that and can't really think of a good way to figure it out... maybe the Cortex-A12 is just terrible at some operation that LZMA uses a lot?) Change-Id: I9f67f7537696ec09496483b16b59a8b73f4cb11b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/234192 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9792 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/southcluster.c')
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