diff options
| author | Martin Roth <martinroth@google.com> | 2017-06-24 21:34:29 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-13 23:54:32 +0000 |
| commit | e6ff1596e7417d24746162b3a567bcb6dd9ef988 (patch) | |
| tree | 36db0c03c6122c9b31d0f25c40a2f5745371a179 /src/soc/intel/baytrail/romstage | |
| parent | fed4303b45aa3c8ba98cd2ab90cf5bf023fc6aae (diff) | |
soc/intel: add IS_ENABLED() around Kconfig symbol references
Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/romstage')
| -rw-r--r-- | src/soc/intel/baytrail/romstage/raminit.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 190231d7c3..f9a5fd1626 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -137,7 +137,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) reset_system(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) if (prev_sleep_state == ACPI_S0) { /* Ensure EC is running RO firmware. */ google_chromeec_check_ec_image(EC_IMAGE_RO); @@ -168,7 +168,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) if (prev_sleep_state != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { - #if CONFIG_HAVE_ACPI_RESUME + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ reset_system(); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index d4571514e5..b6bc64c583 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -21,7 +21,7 @@ #include <cbfs.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #endif #include <elog.h> @@ -128,7 +128,7 @@ void * asmlinkage romstage_main(unsigned long bist, gfx_init(); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); #endif @@ -221,7 +221,7 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) if (prev_sleep_state != ACPI_S3) boot_count_increment(); #endif |