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| author | Jonathan Zhang <jonzhang@meta.com> | 2023-01-30 11:23:04 -0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-22 12:06:39 +0000 |
| commit | 09d2c93c72a80ba4480c62ab710000172348665e (patch) | |
| tree | 777e8384df58755a38273261003dfd47ffdf93bf /src/soc/intel/baytrail/perf_power.c | |
| parent | a0b199c6b4836d1c8f11c2f87e98a5386b69b50f (diff) | |
soc/intel/xeon_sp/uncore.c: Add NCMEM base/limit to map entries
... instead of ME base/limit if the processor is configured with
SOC_INTEL_HAS_NCMEM.
Change-Id: I95783cad1a2d5a3599d120ea0c98e2aa8703bdb4
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72615
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/baytrail/perf_power.c')
0 files changed, 0 insertions, 0 deletions