soc/intel: add IS_ENABLED() around Kconfig symbol references

Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 3 insertions, 3 deletions

diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h
index 1059d3cd6c..b65a3e8d83 100644
--- a/src/soc/intel/baytrail/include/soc/pmc.h
+++ b/src/soc/intel/baytrail/include/soc/pmc.h
@@ -282,7 +282,7 @@ void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
 
-#if CONFIG_ELOG
+#if IS_ENABLED(CONFIG_ELOG)
 void southcluster_log_state(void);
 #else
 static inline void southcluster_log_state(void) {}
diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h
index 824df74cf3..083bf779e7 100644
--- a/src/soc/intel/baytrail/include/soc/ramstage.h
+++ b/src/soc/intel/baytrail/include/soc/ramstage.h
@@ -25,7 +25,7 @@ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config);
 void baytrail_init_cpus(device_t dev);
 void set_max_freq(void);
 void southcluster_enable_dev(device_t dev);
-#if CONFIG_HAVE_REFCODE_BLOB
+#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)
 void baytrail_run_reference_code(void);
 #else
 static inline void baytrail_run_reference_code(void) {}
diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h
index 7913c20ac4..a3f1fc7dac 100644
--- a/src/soc/intel/baytrail/include/soc/romstage.h
+++ b/src/soc/intel/baytrail/include/soc/romstage.h
@@ -41,7 +41,7 @@ void punit_init(void);
 void set_max_freq(void);
 int early_spi_read_wpsr(u8 *sr);
 
-#if CONFIG_ENABLE_BUILTIN_COM1
+#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1)
 void byt_config_com1_and_enable(void);
 #else
 static inline void byt_config_com1_and_enable(void) { }