rambi/baytrail: ACPI, GPIO, audio, misc updates

rambi: Change RAM_ID GPIOs to GPIO_INPUT
Reviewed-on: https://chromium-review.googlesource.com/182934
(cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0)

baytrail: initialize rtc device
Reviewed-on: https://chromium-review.googlesource.com/183051
(cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821)

baytrail: Set SOC power budget values for SdpProfile 2&3
Reviewed-on: https://chromium-review.googlesource.com/183101
(cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55)

baytrail: Set PMC PTPS register correctly
Reviewed-on: https://chromium-review.googlesource.com/183280
(cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad)

baytrail: update to version 809 microcode for c0
Reviewed-on: https://chromium-review.googlesource.com/183256
(cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e)

baytrail: Add a shared GNVS init function
Reviewed-on: https://chromium-review.googlesource.com/183332
(cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c)

baytrail: Add basic support for ACPI System Wake Source
Reviewed-on: https://chromium-review.googlesource.com/183333
(cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619)

baytrail: allow configuration of io hole size
Reviewed-on: https://chromium-review.googlesource.com/183269
(cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919)

baytrail: add in C0 stepping idenitification support.
Reviewed-on: https://chromium-review.googlesource.com/183594
(cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4)

baytrail: add option for enabling PS2 mode
Reviewed-on: https://chromium-review.googlesource.com/183595
(cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f)

rambi: enable PS2 mode for VNN and VCC
Reviewed-on: https://chromium-review.googlesource.com/183596
(cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9)

baytrail: add config option for disabling slp_x stretching
Reviewed-on: https://chromium-review.googlesource.com/183587
(cherry picked from commit f99804c2649bef436644dd300be2a595659ceece)

rambi: disable slp_x stretching after sus fail
Reviewed-on: https://chromium-review.googlesource.com/183588
(cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880)

baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI
Reviewed-on: https://chromium-review.googlesource.com/183597
(cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906)

rambi: fix trackpad and touchscreen wake sources
Reviewed-on: https://chromium-review.googlesource.com/183598
(cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5)

baytrail: Add support for LPE device in ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/184006
(cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f)

rambi: Add LPE GPIOs for Jack/Mic detect
Reviewed-on: https://chromium-review.googlesource.com/184007
(cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578)

rambi: Set TSRx passive threshold to 60C
Reviewed-on: https://chromium-review.googlesource.com/184008
(cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee)

baytrail: DPTF: Add PPCC object for power limit information
Reviewed-on: https://chromium-review.googlesource.com/184158
(cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b)

baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant
Reviewed-on: https://chromium-review.googlesource.com/184442
(cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd)

rambi: Move the CPU passive/critical threshold config to DPTF
Reviewed-on: https://chromium-review.googlesource.com/184443
(cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac)

baytrail: Fix XHCI controller reset on resume
Reviewed-on: https://chromium-review.googlesource.com/184500
(cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd)

baytrail: update lpe audio firmware location
Reviewed-on: https://chromium-review.googlesource.com/184481
(cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6)

rambi: Put LPSS devices in ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/184530
(cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1)

baytrail: initialize HDA device and HDMI codec
Reviewed-on: https://chromium-review.googlesource.com/184710
(cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961)

baytrail: provide GPIO_ACPI_WAKE configuration
Reviewed-on: https://chromium-review.googlesource.com/184718
(cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b)

rambi: configure wake pins as just wake sources
Reviewed-on: https://chromium-review.googlesource.com/184719
(cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115)

baytrail: I2C: Add config data to ACPI Device
Reviewed-on: https://chromium-review.googlesource.com/184922
(cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8)

Squashed 28 commits for rambi and baytrail.

Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6916
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

1 files changed, 121 insertions, 0 deletions

diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c
new file mode 100644
index 0000000000..a99e743a60
--- /dev/null
+++ b/src/soc/intel/baytrail/hda.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <reg_script.h>
+
+#include <baytrail/hda_verb.h>
+#include <baytrail/iomap.h>
+#include <baytrail/iosf.h>
+#include <baytrail/pci_devs.h>
+#include <baytrail/ramstage.h>
+
+static const struct reg_script init_ops[] = {
+	/* Set up VC0 and VC1. */
+	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x24, 0x80000019),
+	REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x28, 0x81000022),
+	/* Enable VCi */
+	REG_PCI_WRITE32(0x120, 0x81000022),
+	/* Enable no snoop traffic. */
+	REG_PCI_OR16(0x78, 1 << 11),
+	/* Configure HDMI codec connection. */
+	REG_PCI_OR32(0xc4, 1 << 1),
+	REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)),
+	REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
+	REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00),
+	/* Configure internal settings. */
+	REG_PCI_OR32(0xc0, 0x7 << 21),
+	REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)),
+	REG_PCI_WRITE32(0xc8, 0x82a30000),
+	REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0),
+	/* Disable docking. */
+	REG_PCI_RMW8(0x4d, ~(1 << 7), 0),
+	REG_SCRIPT_END,
+};
+
+static const uint32_t hdmi_codec_verb_table[] = {
+	/* coreboot specific header */
+	0x80862882, /* vid did for hdmi codec */
+	0x00000000, /* subsystem id */
+	0x00000003, /* number of jacks */
+
+	/* pin widget 5 - port B */
+	0x20471c10,
+	0x20471d00,
+	0x20471e56,
+	0x20471f18,
+
+	/* pin widget 6 - port C */
+	0x20571c20,
+	0x20571d00,
+	0x20571e56,
+	0x20571f18,
+
+	/* pin widget 7 - port D */
+	0x20671c30,
+	0x20671d00,
+	0x20671e56,
+	0x20671f58,
+};
+
+static void hda_init(device_t dev)
+{
+	struct resource *res;
+	int codec_mask;
+	int i;
+
+	reg_script_run_on_dev(dev, init_ops);
+
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (res == NULL)
+		return;
+
+	codec_mask = hda_codec_detect(res->base);
+
+	printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask);
+	if (!codec_mask)
+		return;
+
+	for (i = 3; i >= 0; i--) {
+		if (!((1 << i) & codec_mask))
+			continue;
+		hda_codec_init(res->base, i, sizeof(hdmi_codec_verb_table),
+				hdmi_codec_verb_table);
+	}
+}
+
+static const struct device_operations device_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= hda_init,
+	.enable			= NULL,
+	.scan_bus		= NULL,
+	.ops_pci		= &soc_pci_ops,
+};
+
+static const struct pci_driver southcluster __pci_driver = {
+	.ops		= &device_ops,
+	.vendor		= PCI_VENDOR_ID_INTEL,
+	.device		= HDA_DEVID,
+};