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author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-20 19:17:43 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-23 21:58:34 +0000 |
commit | 47ed2714c8130456ab666b14eb4b5c6f606d559a (patch) | |
tree | 53fe5a7ddf2961dd8716c75ca473ed9a5110c66b /src/soc/intel/baytrail/fadt.c | |
parent | 87a9d8ffe641480c86eb8e856480692748930b8e (diff) |
soc/amd/common/block/acpi/ivrs: conditionally generate eMMC entry
The eMMC entry in the IVRS table should only be generated if an eMMC
controller is present in the SoC.
Where the PCI_DEVFN(0x13, 1) is from is currently unclear to me. There
is no PCI device 0x13 on bus 0 and the eMMC controller is also an MMIO
device and not a PCI device, but this is what the reference code does.
My guess would be that it mainly needs to be a unique PCI device that
won't collide with any existing PCI device in the SoC. Add a comment
about this too.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I00865cb7caf82547e89eb5e77817e3d8ca5d35dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/fadt.c')
0 files changed, 0 insertions, 0 deletions