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| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2019-02-25 10:46:18 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-06 20:06:24 +0000 |
| commit | 46e6852062dfe87281860659034bf20ca16d7aa6 (patch) | |
| tree | 2bfb155d4a767cb246a0bfb0b449837adbcbffcc /src/soc/intel/baytrail/chip.h | |
| parent | 912616941930a352c27a841a735476998e804829 (diff) | |
soc/intel/skylake: Add new Northbridge and IGD IDs
This patch adds support
1) Intel(R) Xeon(R) E3 - 1200/1500 v5/6th Gen Intel(R) Core(TM) Host
Bridge/DRAM Registers - 191F;
2) HD Graphics 530 Skylake GT2 - Intel integrated graphics processor
https://en.wikichip.org/wiki/intel/hd_graphics/530.
This is required to run coreboot on the Intel Core i5-6600 (Skylake)
desktop processor. It has been tested on ASRock H110M-DVS motherboard.
Change-Id: If47e9ac32813a9f73d3a23f44536f60d1003971d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31601
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/chip.h')
0 files changed, 0 insertions, 0 deletions