diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-12 17:46:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-27 10:25:03 +0000 |
| commit | 4abc73183134def757c553aa4eb195fffa824100 (patch) | |
| tree | e6fa253f8e7dc46e80a0a33ea903b4fe0be83419 /src/soc/intel/baytrail/acpi | |
| parent | aeffa86cc551110b62074fa6302f4960d87a9a8c (diff) | |
ACPI: Separate device_nvs_t
Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail/acpi')
| -rw-r--r-- | src/soc/intel/baytrail/acpi/device_nvs.asl | 124 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/acpi/globalnvs.asl | 5 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/acpi/platform.asl | 1 |
3 files changed, 67 insertions, 63 deletions
diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl index 3722856331..aa0e9533f8 100644 --- a/src/soc/intel/baytrail/acpi/device_nvs.asl +++ b/src/soc/intel/baytrail/acpi/device_nvs.asl @@ -1,68 +1,74 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Device Enabled in ACPI Mode */ +External (NVSD) -S0EN, 8, /* SDMA Enable */ -S1EN, 8, /* I2C1 Enable */ -S2EN, 8, /* I2C2 Enable */ -S3EN, 8, /* I2C3 Enable */ -S4EN, 8, /* I2C4 Enable */ -S5EN, 8, /* I2C5 Enable */ -S6EN, 8, /* I2C6 Enable */ -S7EN, 8, /* I2C7 Enable */ -S8EN, 8, /* SDMA2 Enable */ -S9EN, 8, /* SPI Enable */ -SAEN, 8, /* PWM1 Enable */ -SBEN, 8, /* PWM2 Enable */ -SCEN, 8, /* UART2 Enable */ -SDEN, 8, /* UART2 Enable */ -C0EN, 8, /* MMC Enable */ -C1EN, 8, /* SDIO Enable */ -C2EN, 8, /* SD Card Enable */ -LPEN, 8, /* LPE Enable */ +OperationRegion (DNVS, SystemMemory, NVSD, 0x1000) +Field (DNVS, ByteAcc, NoLock, Preserve) +{ + /* Device Enabled in ACPI Mode */ -/* BAR 0 */ + S0EN, 8, /* SDMA Enable */ + S1EN, 8, /* I2C1 Enable */ + S2EN, 8, /* I2C2 Enable */ + S3EN, 8, /* I2C3 Enable */ + S4EN, 8, /* I2C4 Enable */ + S5EN, 8, /* I2C5 Enable */ + S6EN, 8, /* I2C6 Enable */ + S7EN, 8, /* I2C7 Enable */ + S8EN, 8, /* SDMA2 Enable */ + S9EN, 8, /* SPI Enable */ + SAEN, 8, /* PWM1 Enable */ + SBEN, 8, /* PWM2 Enable */ + SCEN, 8, /* UART2 Enable */ + SDEN, 8, /* UART2 Enable */ + C0EN, 8, /* MMC Enable */ + C1EN, 8, /* SDIO Enable */ + C2EN, 8, /* SD Card Enable */ + LPEN, 8, /* LPE Enable */ -S0B0, 32, /* SDMA BAR0 */ -S1B0, 32, /* I2C1 BAR0 */ -S2B0, 32, /* I2C2 BAR0 */ -S3B0, 32, /* I2C3 BAR0 */ -S4B0, 32, /* I2C4 BAR0 */ -S5B0, 32, /* I2C5 BAR0 */ -S6B0, 32, /* I2C6 BAR0 */ -S7B0, 32, /* I2C7 BAR0 */ -S8B0, 32, /* SDMA2 BAR0 */ -S9B0, 32, /* SPI BAR0 */ -SAB0, 32, /* PWM1 BAR0 */ -SBB0, 32, /* PWM2 BAR0 */ -SCB0, 32, /* UART1 BAR0 */ -SDB0, 32, /* UART2 BAR0 */ -C0B0, 32, /* MMC BAR0 */ -C1B0, 32, /* SDIO BAR0 */ -C2B0, 32, /* SD Card BAR0 */ -LPB0, 32, /* LPE BAR0 */ + /* BAR 0 */ -/* BAR 1 */ + S0B0, 32, /* SDMA BAR0 */ + S1B0, 32, /* I2C1 BAR0 */ + S2B0, 32, /* I2C2 BAR0 */ + S3B0, 32, /* I2C3 BAR0 */ + S4B0, 32, /* I2C4 BAR0 */ + S5B0, 32, /* I2C5 BAR0 */ + S6B0, 32, /* I2C6 BAR0 */ + S7B0, 32, /* I2C7 BAR0 */ + S8B0, 32, /* SDMA2 BAR0 */ + S9B0, 32, /* SPI BAR0 */ + SAB0, 32, /* PWM1 BAR0 */ + SBB0, 32, /* PWM2 BAR0 */ + SCB0, 32, /* UART1 BAR0 */ + SDB0, 32, /* UART2 BAR0 */ + C0B0, 32, /* MMC BAR0 */ + C1B0, 32, /* SDIO BAR0 */ + C2B0, 32, /* SD Card BAR0 */ + LPB0, 32, /* LPE BAR0 */ -S0B1, 32, /* SDMA BAR1 */ -S1B1, 32, /* I2C1 BAR1 */ -S2B1, 32, /* I2C2 BAR1 */ -S3B1, 32, /* I2C3 BAR1 */ -S4B1, 32, /* I2C4 BAR1 */ -S5B1, 32, /* I2C5 BAR1 */ -S6B1, 32, /* I2C6 BAR1 */ -S7B1, 32, /* I2C7 BAR1 */ -S8B1, 32, /* SDMA2 BAR1 */ -S9B1, 32, /* SPI BAR1 */ -SAB1, 32, /* PWM1 BAR1 */ -SBB1, 32, /* PWM2 BAR1 */ -SCB1, 32, /* UART1 BAR1 */ -SDB1, 32, /* UART2 BAR1 */ -C0B1, 32, /* MMC BAR1 */ -C1B1, 32, /* SDIO BAR1 */ -C2B1, 32, /* SD Card BAR1 */ -LPB1, 32, /* LPE BAR1 */ + /* BAR 1 */ -/* Extra */ + S0B1, 32, /* SDMA BAR1 */ + S1B1, 32, /* I2C1 BAR1 */ + S2B1, 32, /* I2C2 BAR1 */ + S3B1, 32, /* I2C3 BAR1 */ + S4B1, 32, /* I2C4 BAR1 */ + S5B1, 32, /* I2C5 BAR1 */ + S6B1, 32, /* I2C6 BAR1 */ + S7B1, 32, /* I2C7 BAR1 */ + S8B1, 32, /* SDMA2 BAR1 */ + S9B1, 32, /* SPI BAR1 */ + SAB1, 32, /* PWM1 BAR1 */ + SBB1, 32, /* PWM2 BAR1 */ + SCB1, 32, /* UART1 BAR1 */ + SDB1, 32, /* UART2 BAR1 */ + C0B1, 32, /* MMC BAR1 */ + C1B1, 32, /* SDIO BAR1 */ + C2B1, 32, /* SD Card BAR1 */ + LPB1, 32, /* LPE BAR1 */ -LPFW, 32, /* LPE BAR2 Firmware */ + /* Extra */ + + LPFW, 32, /* LPE BAR2 Firmware */ +} diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index def3fc8f1f..293daa94a3 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -13,7 +13,7 @@ Name(\PICM, 0) /* IOAPIC/8259 */ External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -56,9 +56,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> - - Offset (0x1000), - #include <soc/intel/baytrail/acpi/device_nvs.asl> } /* Set flag to enable USB charging in S3 */ diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl index 67b515ab86..143327684d 100644 --- a/src/soc/intel/baytrail/acpi/platform.asl +++ b/src/soc/intel/baytrail/acpi/platform.asl @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/intel/baytrail/acpi/device_nvs.asl> #include <southbridge/intel/common/acpi/platform.asl> /* |