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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-08 15:28:40 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-11 14:18:44 +0000 |
| commit | cdbfa6e63788a7c71e3167378657d0afb8beab53 (patch) | |
| tree | 55a9050892b0eab86db728f34f5d22c5a65485b8 /src/soc/intel/baytrail/acpi/platform.asl | |
| parent | b0947172c889623a26d849e7d732990f122f9805 (diff) | |
soc/amd/common/block/include/espi: rename IO/MMIO base/size registers
This aligns the register names more with the PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail/acpi/platform.asl')
0 files changed, 0 insertions, 0 deletions