diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-08-26 15:29:58 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-02 07:17:25 +0000 |
| commit | ac1b1dd83e0a509f94bd75f42128de469fd868d7 (patch) | |
| tree | 7011fee60d03163f3153ef3964052b42a6ee7ac3 /src/soc/intel/baytrail/acpi/lpss.asl | |
| parent | 26058dca96d928ececf488286112cb1590f7b61e (diff) | |
util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH
This patch performs below operations:
1. Remove reserved NR field from Gen 5 onwards SPI programming guide
2. Convert ISL to PSL as applicable for Gen 5 onwards PCH
3. Skip FLMAP2 register dump due to nonuniformity since Gen 5 onwards PCH
4. Dump FLILL1 register as applicable for Gen 5 onwards PCH
5. Remove FLPB register as not applicable since Gen 5 PCH
BUG=b:153888802
TEST=Dump FD for Hatch platform as below
> ifdtool -d coreboot.rom
PCH Revision: 300 series Cannon Point/ 400 series Ice Point
FLMAP0: 0x00040003
FRBA: 0x40
NC: 1
FCBA: 0x30
FLMAP1: 0x45100208
PSL: 0x45
FPSBA: 0x100
NM: 2
FMBA: 0x80
FLILL1 0xc7c4b9b7
Invalid Instruction 7: 0xc7
Invalid Instruction 6: 0xc4
Invalid Instruction 5: 0xb9
Invalid Instruction 4: 0xb7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail/acpi/lpss.asl')
0 files changed, 0 insertions, 0 deletions