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| author | Subrata Banik <subratabanik@google.com> | 2023-02-01 17:19:50 +0530 |
|---|---|---|
| committer | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2023-02-02 11:38:33 +0000 |
| commit | 794137e2a82eca7e7b2428759007155243009720 (patch) | |
| tree | 39cd2f8b7ad97b84ddb0a0213a8b97a7391a78d3 /src/soc/intel/baytrail/acpi/lpss.asl | |
| parent | b184e6e0a1ccd1d2cb2cc53d06f7969c98cca899 (diff) | |
soc/intel/meteorlake: Enable V1p05-PHY supply external FET control
This patch enables S0i2.2 by letting 1.5V Phy supply to control the
externa FET.
BUG=b:256805904
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8771c11ce3b305343c7e96510e1375538d5e7f04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72709
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/soc/intel/baytrail/acpi/lpss.asl')
0 files changed, 0 insertions, 0 deletions