diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-01 14:36:03 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-03-11 19:54:58 +0100 |
| commit | 97651c55a3058bfedacdeb6de6243087d1dc5b7a (patch) | |
| tree | 5dffb3256522b47ff9eb4c69042074f5464055c5 /src/soc/intel/baytrail/Makefile.inc | |
| parent | 65ad521f8a19ec42c1bafa6777eb927fa55261a2 (diff) | |
baytrail: add audio clock workaround for LPE
Apparently the LPE device needs a 25MHz clock. Provide
the work around to enable this clock.
BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted. Confirmed setting being applied.
Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175493
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4928
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/Makefile.inc')
| -rw-r--r-- | src/soc/intel/baytrail/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index d41405766e..2149e975ce 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -35,6 +35,7 @@ ramstage-y += southcluster.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c ramstage-y += sata.c ramstage-y += acpi.c +ramstage-y += lpe.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c |