From 97651c55a3058bfedacdeb6de6243087d1dc5b7a Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 1 Nov 2013 14:36:03 -0500 Subject: baytrail: add audio clock workaround for LPE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apparently the LPE device needs a 25MHz clock. Provide the work around to enable this clock. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted. Confirmed setting being applied. Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/175493 Reviewed-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/4928 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/baytrail/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/baytrail/Makefile.inc') diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index d41405766e..2149e975ce 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -35,6 +35,7 @@ ramstage-y += southcluster.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c ramstage-y += sata.c ramstage-y += acpi.c +ramstage-y += lpe.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c -- cgit v1.2.3