diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-10-07 16:24:44 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-11 22:18:59 +0100 |
| commit | 08a4613219f5a26a2bcf1216deeb08284cb5269a (patch) | |
| tree | 0bda3f6be049135af087a205cf7c739facdfb718 /src/soc/intel/baytrail/Kconfig | |
| parent | 3f5a1ffb83895b325ec54ba0a6d0147f0af5fca8 (diff) | |
baytrail: adjust cache policy during romstage
The caching policy for romstage was previously using a 32KiB
of cache-as-ram for both the MRC wrapper and the romstage stack/data.
It also used a 32KiB code cache region. The BWG's limitations for
the code and data region before memory is up was wrong. It consists
of a 16-way set associative 1MiB cache. As long as enough addresses
are not read there isn't a risk of evicting the data/stack.
Now create a 64KiB cache-as-ram region split evenly between romstage
and the MRC wrapper. Additionally cache the memory just below
4GiB in CBFS size. This will cover any code and read-only data needed.
BUG=chrome-os-partner:22858
BRANCH=None
TEST=Built and booted quickly with corresponding changes to MRC warpper.
CQ-DEPEND=CL:*146175
Change-Id: I021cecb886a9c0622005edc389136d22905d4520
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172150
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4868
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/Kconfig')
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 15 |
1 files changed, 3 insertions, 12 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 613593edb7..4cd21334fc 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -92,15 +92,6 @@ endif # CACHE_MRC_SETTINGS endif # HAVE_MRC -config CAR_TILE_SIZE - hex - default 0x8000 - help - The tile size is the limit that can be assigned to cache-as-ram - region as well as the amount of code cache used during cache-as-ram. - Also note that (DCACHE_RAM_BASE ^ MRC_BIN_ADDRESS) & CAR_TILE_SIZE == - CAR_TILE_SIZE. - # Cache As RAM region layout: # # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE @@ -123,11 +114,11 @@ config CAR_TILE_SIZE config DCACHE_RAM_BASE hex - default 0xff7f8000 + default 0xff800000 config DCACHE_RAM_SIZE hex - default 0x1000 + default 0x8000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE @@ -135,7 +126,7 @@ config DCACHE_RAM_SIZE config DCACHE_RAM_MRC_VAR_SIZE hex - default 0x7000 + default 0x8000 help The amount of cache-as-ram region required by the reference code. |