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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-04 14:48:05 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-21 07:14:00 +0000
commitdadcbfbe8c682c89b277fdbdfdd26cabd15fc20a (patch)
tree34382c8a51e3a496a3acbd9f0b198c520ef97d9a /src/soc/intel/apollolake
parentfe6070f7280cfcc41fffded67789439531e8ab49 (diff)
soc/intel: convert XTAL frequency constant to Kconfig
This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/Kconfig3
-rw-r--r--src/soc/intel/apollolake/include/soc/cpu.h3
-rw-r--r--src/soc/intel/apollolake/pmutil.c12
3 files changed, 10 insertions, 8 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index c1b5252aa8..69d42bdf19 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -157,6 +157,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
int
default 100
+config CPU_XTAL_HZ
+ default 19200000
+
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 133
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 490820c3f6..38b830a16f 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -6,9 +6,6 @@
#include <cpu/x86/msr.h>
#include <intelblocks/msr.h>
-/* Common Timer Copy (CTC) frequency - 19.2MHz. */
-#define CTC_FREQ 19200000
-
struct device;
void apollolake_init_cpus(struct device *dev);
void mainboard_devtree_update(struct device *dev);
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index c6d2eec791..e0de93eae4 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -180,15 +180,17 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
void enable_pm_timer_emulation(void)
{
- /* ACPI PM timer emulation */
msr_t msr;
+
+ if (!CONFIG_CPU_XTAL_HZ)
+ return;
+
/*
* The derived frequency is calculated as follows:
- * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer
- * frequency is used.
+ * (clock * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
*/
- msr.hi = (3579545ULL << 32) / CTC_FREQ;
+ msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
/* Set PM1 timer IO port and enable */
msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR);
wrmsr(MSR_EMULATE_PM_TIMER, msr);