soc/intel/apollolake: Use the new SPI driver interface

1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash controller
in different files.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully for reef.

Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17562
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

8 files changed, 436 insertions, 403 deletions

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 24b5035bed..d058ddbbba 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -12,6 +12,7 @@ bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/cache_as_ram.S
 bootblock-y += bootblock/bootblock.c
 bootblock-y += car.c
+bootblock-y += flash_ctrlr.c
 bootblock-y += gpio.c
 bootblock-y += heci.c
 bootblock-y += itss.c
@@ -24,6 +25,7 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 
 romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
+romstage-y += flash_ctrlr.c
 romstage-y += gpio.c
 romstage-y += heci.c
 romstage-y += i2c_early.c
@@ -38,6 +40,7 @@ romstage-y += pmutil.c
 romstage-y += reset.c
 romstage-y += spi.c
 
+smm-y += flash_ctrlr.c
 smm-y += mmap_boot.c
 smm-y += pmutil.c
 smm-y += gpio.c
@@ -50,6 +53,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += cpu.c
 ramstage-y += chip.c
 ramstage-y += elog.c
+ramstage-y += flash_ctrlr.c
 ramstage-y += dsp.c
 ramstage-y += gpio.c
 ramstage-y += graphics.c
@@ -76,6 +80,7 @@ ramstage-y += spi.c
 ramstage-y += xhci.c
 
 postcar-y += exit_car.S
+postcar-y += flash_ctrlr.c
 postcar-y += memmap.c
 postcar-y += mmap_boot.c
 postcar-y += spi.c
@@ -83,6 +88,7 @@ postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 postcar-y += tsc_freq.c
 
 verstage-y += car.c
+verstage-y += flash_ctrlr.c
 verstage-y += i2c_early.c
 verstage-y += heci.c
 verstage-y += memmap.c
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index be10a22736..1f5055d6a3 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -21,6 +21,7 @@
 #include <lib.h>
 #include <soc/iomap.h>
 #include <soc/cpu.h>
+#include <soc/flash_ctrlr.h>
 #include <soc/gpio.h>
 #include <soc/iosf.h>
 #include <soc/mmap_boot.h>
@@ -129,7 +130,7 @@ static void enable_spibar(void)
 	pci_write_config8(dev, PCI_COMMAND, val);
 
 	/* Initialize SPI to allow BIOS to write/erase on flash. */
-	spi_init();
+	spi_flash_init();
 }
 
 static void enable_pmcbar(void)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 32d68cc9ad..d481f3e891 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -28,6 +28,7 @@
 #include <romstage_handoff.h>
 #include <soc/iomap.h>
 #include <soc/cpu.h>
+#include <soc/flash_ctrlr.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/nvs.h>
@@ -497,14 +498,14 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase)
 }
 
 /*
- * spi_init() needs to run unconditionally on every boot (including resume) to
- * allow write protect to be disabled for eventlog and nvram updates. This needs
- * to be done as early as possible in ramstage. Thus, add a callback for entry
- * into BS_PRE_DEVICE.
+ * spi_flash init() needs to run unconditionally on every boot (including
+ * resume) to allow write protect to be disabled for eventlog and nvram
+ * updates. This needs to be done as early as possible in ramstage. Thus, add a
+ * callback for entry into BS_PRE_DEVICE.
  */
-static void spi_init_cb(void *unused)
+static void spi_flash_init_cb(void *unused)
 {
-	spi_init();
+	spi_flash_init();
 }
 
-BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_init_cb, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);
diff --git a/src/soc/intel/apollolake/flash_ctrlr.c b/src/soc/intel/apollolake/flash_ctrlr.c
new file mode 100644
index 0000000000..a608ca700c
--- /dev/null
+++ b/src/soc/intel/apollolake/flash_ctrlr.c
@@ -0,0 +1,390 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include <arch/early_variables.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/flash_ctrlr.h>
+#include <soc/intel/common/spi_flash.h>
+#include <soc/pci_devs.h>
+#include <spi_flash.h>
+#include <spi-generic.h>
+#include <stdlib.h>
+#include <string.h>
+
+/* Helper to create a SPI context on API entry. */
+#define BOILERPLATE_CREATE_CTX(ctx)		\
+	struct spi_flash_ctx	real_ctx;	\
+	struct spi_flash_ctx *ctx = &real_ctx;	\
+	_get_spi_flash_ctx(ctx)
+
+/*
+ * Anything that's not success is <0. Provided solely for readability, as these
+ * constants are not used outside this file.
+ */
+enum errors {
+	SUCCESS			= 0,
+	E_NOT_IMPLEMENTED	= -1,
+	E_TIMEOUT		= -2,
+	E_HW_ERROR		= -3,
+	E_ARGUMENT		= -4,
+};
+
+/* Reduce data-passing burden by grouping transaction data in a context. */
+struct spi_flash_ctx {
+	uintptr_t mmio_base;
+	device_t pci_dev;
+	uint32_t hsfsts_on_last_error;
+};
+
+static void _get_spi_flash_ctx(struct spi_flash_ctx *ctx)
+{
+	uint32_t bar;
+
+	/* FIXME: use device definition */
+	ctx->pci_dev = SPI_DEV;
+
+	bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0);
+	ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+	ctx->hsfsts_on_last_error = 0;
+}
+
+/* Read register from the SPI flash controller. 'reg' is the register offset. */
+static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx, uint16_t reg)
+{
+	uintptr_t addr =  ALIGN_DOWN(ctx->mmio_base + reg, 4);
+	return read32((void *)addr);
+}
+
+uint32_t spi_flash_ctrlr_reg_read(uint16_t reg)
+{
+	BOILERPLATE_CREATE_CTX(ctx);
+	return _spi_flash_ctrlr_reg_read(ctx, reg);
+}
+
+/* Write to register in SPI flash controller. 'reg' is the register offset. */
+static void _spi_flash_ctrlr_reg_write(struct spi_flash_ctx *ctx, uint16_t reg,
+				       uint32_t val)
+{
+	uintptr_t addr =  ALIGN_DOWN(ctx->mmio_base + reg, 4);
+	write32((void *)addr, val);
+
+}
+
+/*
+ * The hardware datasheet is not clear on what HORD values actually do. It
+ * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which
+ * is the signature and revision fields. HORD_JEDEC provides access to the
+ * actual flash parameters, and is most likely what you want to use when
+ * probing the flash from software.
+ * It's okay to rely on SFPD, since the SPI flash controller requires an SFDP
+ * 1.5 or newer compliant SPI flash chip.
+ * NOTE: Due to the register layout of the hardware, all accesses will be
+ * aligned to a 4 byte boundary.
+ */
+static uint32_t read_spi_flash_sfdp_param(struct spi_flash_ctx *ctx,
+					  uint16_t sfdp_reg)
+{
+	uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK;
+	_spi_flash_ctrlr_reg_write(ctx, SPIBAR_PTINX,
+				   ptinx_index | SPIBAR_PTINX_HORD_JEDEC);
+	return _spi_flash_ctrlr_reg_read(ctx, SPIBAR_PTDATA);
+}
+
+/* Fill FDATAn FIFO in preparation for a write transaction. */
+static void fill_xfer_fifo(struct spi_flash_ctx *ctx, const void *data,
+			   size_t len)
+{
+	len = min(len, SPIBAR_FDATA_FIFO_SIZE);
+
+	/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
+	memcpy((void*)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len);
+}
+
+/* Drain FDATAn FIFO after a read transaction populates data. */
+static void drain_xfer_fifo(struct spi_flash_ctx *ctx, void *dest, size_t len)
+{
+	len = min(len, SPIBAR_FDATA_FIFO_SIZE);
+
+	/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
+	memcpy(dest, (void*)(ctx->mmio_base + SPIBAR_FDATA(0)), len);
+}
+
+/* Fire up a transfer using the hardware sequencer. */
+static void start_hwseq_xfer(struct spi_flash_ctx *ctx, uint32_t hsfsts_cycle,
+				 uint32_t flash_addr, size_t len)
+{
+	/* Make sure all W1C status bits get cleared. */
+	uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS;
+	/* Set up transaction parameters. */
+	hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK;
+	hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1);
+
+	_spi_flash_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr);
+	_spi_flash_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL,
+			     hsfsts | SPIBAR_HSFSTS_FGO);
+}
+
+static void print_xfer_error(struct spi_flash_ctx *ctx,
+			     const char *failure_reason, uint32_t flash_addr)
+{
+	printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n"
+			 "\tHSFSTS = 0x%08x\n",
+	       failure_reason, flash_addr, ctx->hsfsts_on_last_error);
+}
+
+static int wait_for_hwseq_xfer(struct spi_flash_ctx *ctx)
+{
+	uint32_t hsfsts;
+	do {
+		hsfsts = _spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL);
+
+		if (hsfsts & SPIBAR_HSFSTS_FCERR) {
+			ctx->hsfsts_on_last_error = hsfsts;
+			return E_HW_ERROR;
+		}
+	/* TODO: set up timer and abort on timeout */
+	} while (!(hsfsts & SPIBAR_HSFSTS_FDONE));
+
+	return SUCCESS;
+}
+
+/* Execute SPI flash transfer. This is a blocking call. */
+static int exec_sync_hwseq_xfer(struct spi_flash_ctx *ctx,
+				uint32_t hsfsts_cycle, uint32_t flash_addr,
+				size_t len)
+{
+	int ret;
+	start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len);
+	ret = wait_for_hwseq_xfer(ctx);
+	if (ret != SUCCESS) {
+		const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error";
+		print_xfer_error(ctx, reason, flash_addr);
+	}
+	return ret;
+}
+
+unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+{
+	return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE);
+}
+
+/*
+ * Write-protection status for BIOS region (BIOS_CONTROL register):
+ * EISS/WPD bits	00	01	10	11
+ * 			--	--	--	--
+ * normal mode		RO	RW	RO	RO
+ * SMM mode		RO	RW	RO	RW
+ */
+void spi_flash_init(void)
+{
+	uint32_t bios_ctl;
+
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL);
+	bios_ctl |= SPIBAR_BIOS_CONTROL_WPD;
+	bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS;
+
+	/* Enable Prefetching and caching. */
+	bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE;
+	bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE;
+
+	pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl);
+}
+
+/* Flash device operations. */
+static struct spi_flash boot_flash CAR_GLOBAL;
+
+static int nuclear_spi_flash_erase(const struct spi_flash *flash,
+				uint32_t offset, size_t len)
+{
+	int ret;
+	size_t erase_size;
+	uint32_t erase_cycle;
+
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) {
+		printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n");
+		return E_ARGUMENT;
+	}
+
+	while (len) {
+		if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) {
+			erase_size = 64 * KiB;
+			erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE;
+		} else {
+			erase_size = 4 * KiB;
+			erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE;
+		}
+		printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n",
+		       offset, erase_size / KiB);
+
+		ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0);
+		if (ret != SUCCESS)
+			return ret;
+
+		offset += erase_size;
+		len -= erase_size;
+	}
+
+	return SUCCESS;
+}
+
+/*
+ * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
+ * that the operation does not cross 256-byte boundary.
+ */
+static size_t get_xfer_len(uint32_t addr, size_t len)
+{
+	size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
+	size_t bytes_left = ALIGN_UP(addr, 256) - addr;
+
+	if (bytes_left)
+		xfer_len = min(xfer_len, bytes_left);
+
+	return xfer_len;
+}
+
+static int nuclear_spi_flash_read(const struct spi_flash *flash, uint32_t addr,
+				size_t len, void *buf)
+{
+	int ret;
+	size_t xfer_len;
+	uint8_t *data = buf;
+
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	while (len) {
+		xfer_len = get_xfer_len(addr, len);
+
+		ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ,
+						addr, xfer_len);
+		if (ret != SUCCESS)
+			return ret;
+
+		drain_xfer_fifo(ctx, data, xfer_len);
+
+		addr += xfer_len;
+		data += xfer_len;
+		len -= xfer_len;
+	}
+
+	return SUCCESS;
+}
+
+static int nuclear_spi_flash_write(const struct spi_flash *flash, uint32_t addr,
+				size_t len, const void *buf)
+{
+	int ret;
+	size_t xfer_len;
+	const uint8_t *data = buf;
+
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	while (len) {
+		xfer_len = get_xfer_len(addr, len);
+		fill_xfer_fifo(ctx, data, xfer_len);
+
+		ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE,
+						addr, xfer_len);
+		if (ret != SUCCESS)
+			return ret;
+
+		addr += xfer_len;
+		data += xfer_len;
+		len -= xfer_len;
+	}
+
+	return SUCCESS;
+}
+
+static int nuclear_spi_flash_status(const struct spi_flash *flash, uint8_t *reg)
+{
+	int ret;
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0,
+				   sizeof(*reg));
+	if (ret != SUCCESS)
+		return ret;
+
+	drain_xfer_fifo(ctx, reg, sizeof(*reg));
+	return ret;
+}
+
+/*
+ * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did.
+ * For details see:
+ * Ch 31, SPI: p. 194
+ * The size of the flash component is always taken from density field in the
+ * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller.
+ */
+struct spi_flash *spi_flash_programmer_probe(struct spi_slave *dev, int force)
+{
+	BOILERPLATE_CREATE_CTX(ctx);
+	struct spi_flash *flash;
+	uint32_t flash_bits;
+
+	flash = car_get_var_ptr(&boot_flash);
+
+	/*
+	 * bytes = (bits + 1) / 8;
+	 * But we need to do the addition in a way which doesn't overflow for
+	 * 4 Gbit devices (flash_bits == 0xffffffff).
+	 */
+	/* FIXME: Don't hardcode 0x04 ? */
+	flash_bits = read_spi_flash_sfdp_param(ctx, 0x04);
+	flash->size = (flash_bits >> 3) + 1;
+
+	memcpy(&flash->spi, dev, sizeof(*dev));
+	flash->name = "Apollolake hardware sequencer";
+
+	/* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */
+	flash->sector_size = 4 * KiB;
+	/*
+	 * FIXME: Get erase+cmd, and status_cmd from SFDP.
+	 *
+	 * flash->erase_cmd = ???
+	 * flash->status_cmd = ???
+	 */
+
+	flash->internal_write = nuclear_spi_flash_write;
+	flash->internal_erase = nuclear_spi_flash_erase;
+	flash->internal_read = nuclear_spi_flash_read;
+	flash->internal_status = nuclear_spi_flash_status;
+
+	return flash;
+}
+
+int spi_flash_get_fpr_info(struct fpr_info *info)
+{
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	if (!ctx->mmio_base)
+		return -1;
+
+	info->base = ctx->mmio_base + SPIBAR_FPR_BASE;
+	info->max = SPIBAR_FPR_MAX;
+
+	return 0;
+}
diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h
index 4f16a85717..5b9c6222b3 100644
--- a/src/soc/intel/apollolake/include/soc/spi.h
+++ b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h
@@ -84,8 +84,10 @@
  * Reads status register. On success returns 0 and status contains the value
  * read from the status register. On error returns -1.
  */
-int spi_read_status(uint8_t *status);
+int spi_flash_read_status(uint8_t *status);
 
 /* Read SPI controller register. */
-uint32_t spi_ctrlr_reg_read(uint16_t reg);
+uint32_t spi_flash_ctrlr_reg_read(uint16_t reg);
+
+void spi_flash_init(void);
 #endif
diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c
index bf2e5b95b4..7159c24f52 100644
--- a/src/soc/intel/apollolake/mmap_boot.c
+++ b/src/soc/intel/apollolake/mmap_boot.c
@@ -22,9 +22,9 @@
 #include <commonlib/region.h>
 #include <console/console.h>
 #include <fmap.h>
+#include <soc/flash_ctrlr.h>
 #include <soc/intel/common/nvm.h>
 #include <soc/mmap_boot.h>
-#include <soc/spi.h>
 
 /*
  * BIOS region on the flash is mapped right below 4GiB in the address
@@ -81,7 +81,7 @@ static void bios_mmap_init(void)
 	 * Base and Limit.
 	 * Base and Limit fields are in units of 4KiB.
 	 */
-	uint32_t val = spi_ctrlr_reg_read(SPIBAR_BIOS_BFPREG);
+	uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BIOS_BFPREG);
 
 	start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB;
 	bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 039b586263..77562c4699 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -32,14 +32,15 @@
 #include <fsp/memmap.h>
 #include <fsp/util.h>
 #include <soc/cpu.h>
+#include <soc/flash_ctrlr.h>
 #include <soc/intel/common/mrc_cache.h>
 #include <soc/iomap.h>
 #include <soc/northbridge.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
-#include <soc/spi.h>
 #include <soc/uart.h>
+#include <spi_flash.h>
 #include <string.h>
 #include <timestamp.h>
 #include <timer.h>
@@ -316,7 +317,12 @@ void mainboard_save_dimm_info(void)
 int get_sw_write_protect_state(void)
 {
 	uint8_t status;
+	struct spi_flash *flash;
+
+	flash = spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0);
+	if (!flash)
+		return 0;
 
 	/* Return unprotected status if status read fails. */
-	return spi_read_status(&status) ? 0 : !!(status & 0x80);
+	return spi_flash_status(flash, &status) ? 0 : !!(status & 0x80);
 }
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c
index f9c17cdc2a..87d4d01241 100644
--- a/src/soc/intel/apollolake/spi.c
+++ b/src/soc/intel/apollolake/spi.c
@@ -1,8 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2016 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ * Copyright 2016 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,401 +14,29 @@
  * GNU General Public License for more details.
  */
 
-#define __SIMPLE_DEVICE__
-
-#include <arch/early_variables.h>
-#include <arch/io.h>
 #include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <soc/intel/common/spi_flash.h>
-#include <soc/pci_devs.h>
-#include <soc/spi.h>
-#include <spi_flash.h>
 #include <spi-generic.h>
-#include <stdlib.h>
-#include <string.h>
-
-/* Helper to create a SPI context on API entry. */
-#define BOILERPLATE_CREATE_CTX(ctx)		\
-	struct spi_ctx	real_ctx;		\
-	struct spi_ctx *ctx = &real_ctx;	\
-	_spi_get_ctx(ctx)
-
-/*
- * Anything that's not success is <0. Provided solely for readability, as these
- * constants are not used outside this file.
- */
-enum errors {
-	SUCCESS			= 0,
-	E_NOT_IMPLEMENTED	= -1,
-	E_TIMEOUT		= -2,
-	E_HW_ERROR		= -3,
-	E_ARGUMENT		= -4,
-};
-
-/* Reduce data-passing burden by grouping transaction data in a context. */
-struct spi_ctx {
-	uintptr_t mmio_base;
-	device_t pci_dev;
-	uint32_t hsfsts_on_last_error;
-};
-
-static void _spi_get_ctx(struct spi_ctx *ctx)
-{
-	uint32_t bar;
-
-	/* FIXME: use device definition */
-	ctx->pci_dev = SPI_DEV;
 
-	bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0);
-	ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
-	ctx->hsfsts_on_last_error = 0;
-}
-
-/* Read register from the SPI controller. 'reg' is the register offset. */
-static uint32_t _spi_ctrlr_reg_read(struct spi_ctx *ctx, uint16_t reg)
+/* SPI controller managing the fast SPI. */
+static int fast_spi_ctrlr_setup(const struct spi_slave *dev)
 {
-	uintptr_t addr =  ALIGN_DOWN(ctx->mmio_base + reg, 4);
-	return read32((void *)addr);
-}
-
-uint32_t spi_ctrlr_reg_read(uint16_t reg)
-{
-	BOILERPLATE_CREATE_CTX(ctx);
-	return _spi_ctrlr_reg_read(ctx, reg);
-}
-
-/* Write to register in the SPI controller. 'reg' is the register offset. */
-static void _spi_ctrlr_reg_write(struct spi_ctx *ctx, uint16_t reg,
-				 uint32_t val)
-{
-	uintptr_t addr =  ALIGN_DOWN(ctx->mmio_base + reg, 4);
-	write32((void *)addr, val);
-
-}
-
-/*
- * The hardware datasheet is not clear on what HORD values actually do. It
- * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which
- * is the signature and revision fields. HORD_JEDEC provides access to the
- * actual flash parameters, and is most likely what you want to use when
- * probing the flash from software.
- * It's okay to rely on SFPD, since the SPI controller requires an SFDP 1.5 or
- * newer compliant SPI chip.
- * NOTE: Due to the register layout of the hardware, all accesses will be
- * aligned to a 4 byte boundary.
- */
-static uint32_t read_spi_sfdp_param(struct spi_ctx *ctx, uint16_t sfdp_reg)
-{
-	uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK;
-	_spi_ctrlr_reg_write(ctx, SPIBAR_PTINX,
-			     ptinx_index | SPIBAR_PTINX_HORD_JEDEC);
-	return _spi_ctrlr_reg_read(ctx, SPIBAR_PTDATA);
-}
-
-/* Fill FDATAn FIFO in preparation for a write transaction. */
-static void fill_xfer_fifo(struct spi_ctx *ctx, const void *data, size_t len)
-{
-	len = min(len, SPIBAR_FDATA_FIFO_SIZE);
-
-	/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
-	memcpy((void*)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len);
-}
-
-/* Drain FDATAn FIFO after a read transaction populates data. */
-static void drain_xfer_fifo(struct spi_ctx *ctx, void *dest, size_t len)
-{
-	len = min(len, SPIBAR_FDATA_FIFO_SIZE);
-
-	/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
-	memcpy(dest, (void*)(ctx->mmio_base + SPIBAR_FDATA(0)), len);
-}
-
-/* Fire up a transfer using the hardware sequencer. */
-static void start_hwseq_xfer(struct spi_ctx *ctx, uint32_t hsfsts_cycle,
-				 uint32_t flash_addr, size_t len)
-{
-	/* Make sure all W1C status bits get cleared. */
-	uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS;
-	/* Set up transaction parameters. */
-	hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK;
-	hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1);
-
-	_spi_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr);
-	_spi_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL,
-			     hsfsts | SPIBAR_HSFSTS_FGO);
-}
-
-static void print_xfer_error(struct spi_ctx *ctx, const char *failure_reason,
-			     uint32_t flash_addr)
-{
-	printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n"
-			 "\tHSFSTS = 0x%08x\n",
-	       failure_reason, flash_addr, ctx->hsfsts_on_last_error);
-}
-
-static int wait_for_hwseq_xfer(struct spi_ctx *ctx)
-{
-	uint32_t hsfsts;
-	do {
-		hsfsts = _spi_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL);
-
-		if (hsfsts & SPIBAR_HSFSTS_FCERR) {
-			ctx->hsfsts_on_last_error = hsfsts;
-			return E_HW_ERROR;
-		}
-	/* TODO: set up timer and abort on timeout */
-	} while (!(hsfsts & SPIBAR_HSFSTS_FDONE));
-
-	return SUCCESS;
-}
-
-/* Execute SPI transfer. This is a blocking call. */
-static int exec_sync_hwseq_xfer(struct spi_ctx *ctx, uint32_t hsfsts_cycle,
-				 uint32_t flash_addr, size_t len)
-{
-	int ret;
-	start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len);
-	ret = wait_for_hwseq_xfer(ctx);
-	if (ret != SUCCESS) {
-		const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error";
-		print_xfer_error(ctx, reason, flash_addr);
-	}
-	return ret;
-}
-
-unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
-{
-	return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE);
-}
-
-/*
- * Write-protection status for BIOS region (BIOS_CONTROL register):
- * EISS/WPD bits	00	01	10	11
- * 			--	--	--	--
- * normal mode		RO	RW	RO	RO
- * SMM mode		RO	RW	RO	RW
- */
-void spi_init(void)
-{
-	uint32_t bios_ctl;
-
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL);
-	bios_ctl |= SPIBAR_BIOS_CONTROL_WPD;
-	bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS;
-
-	/* Enable Prefetching and caching. */
-	bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE;
-	bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE;
-
-	pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl);
-}
-
-static int nuclear_spi_erase(const struct spi_flash *flash, uint32_t offset,
-			     size_t len)
-{
-	int ret;
-	size_t erase_size;
-	uint32_t erase_cycle;
-
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) {
-		printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n");
-		return E_ARGUMENT;
-	}
-
-	while (len) {
-		if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) {
-			erase_size = 64 * KiB;
-			erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE;
-		} else {
-			erase_size = 4 * KiB;
-			erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE;
-		}
-		printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n",
-		       offset, erase_size / KiB);
-
-		ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0);
-		if (ret != SUCCESS)
-			return ret;
-
-		offset += erase_size;
-		len -= erase_size;
-	}
-
-	return SUCCESS;
-}
-
-/*
- * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
- * that the operation does not cross 256-byte boundary.
- */
-static size_t get_xfer_len(uint32_t addr, size_t len)
-{
-	size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
-	size_t bytes_left = ALIGN_UP(addr, 256) - addr;
-
-	if (bytes_left)
-		xfer_len = min(xfer_len, bytes_left);
-
-	return xfer_len;
-}
-
-static int nuclear_spi_read(const struct spi_flash *flash, uint32_t addr,
-			size_t len, void *buf)
-{
-	int ret;
-	size_t xfer_len;
-	uint8_t *data = buf;
-
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	while (len) {
-		xfer_len = get_xfer_len(addr, len);
-
-		ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ,
-						addr, xfer_len);
-		if (ret != SUCCESS)
-			return ret;
-
-		drain_xfer_fifo(ctx, data, xfer_len);
-
-		addr += xfer_len;
-		data += xfer_len;
-		len -= xfer_len;
-	}
-
-	return SUCCESS;
-}
-
-static int nuclear_spi_write(const struct spi_flash *flash, uint32_t addr,
-			size_t len, const void *buf)
-{
-	int ret;
-	size_t xfer_len;
-	const uint8_t *data = buf;
-
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	while (len) {
-		xfer_len = get_xfer_len(addr, len);
-		fill_xfer_fifo(ctx, data, xfer_len);
-
-		ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE,
-						addr, xfer_len);
-		if (ret != SUCCESS)
-			return ret;
-
-		addr += xfer_len;
-		data += xfer_len;
-		len -= xfer_len;
-	}
-
-	return SUCCESS;
-}
-
-static int nuclear_spi_status(const struct spi_flash *flash, uint8_t *reg)
-{
-	int ret;
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0,
-				   sizeof(*reg));
-	if (ret != SUCCESS)
-		return ret;
-
-	drain_xfer_fifo(ctx, reg, sizeof(*reg));
-	return ret;
-}
-
-static struct spi_flash boot_flash CAR_GLOBAL;
-
-/*
- * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did.
- * For details see:
- * Ch 31, SPI: p. 194
- * The size of the flash component is always taken from density field in the
- * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller.
- */
-struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force)
-{
-	BOILERPLATE_CREATE_CTX(ctx);
-	struct spi_flash *flash;
-	uint32_t flash_bits;
-
-	flash = car_get_var_ptr(&boot_flash);
-
-	/*
-	 * bytes = (bits + 1) / 8;
-	 * But we need to do the addition in a way which doesn't overflow for
-	 * 4 Gbit devices (flash_bits == 0xffffffff).
-	 */
-	/* FIXME: Don't hardcode 0x04 ? */
-	flash_bits = read_spi_sfdp_param(ctx, 0x04);
-	flash->size = (flash_bits >> 3) + 1;
-
-	memcpy(&flash->spi, spi, sizeof(*spi));
-
-	flash->name = "Apollolake hardware sequencer";
-
-	/* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */
-	flash->sector_size = 4 * KiB;
-	/*
-	 * FIXME: Get erase+cmd, and status_cmd from SFDP.
-	 *
-	 * flash->erase_cmd = ???
-	 * flash->status_cmd = ???
-	 */
-
-	flash->internal_write = nuclear_spi_write;
-	flash->internal_erase = nuclear_spi_erase;
-	flash->internal_read = nuclear_spi_read;
-	flash->internal_status = nuclear_spi_status;
-
-	return flash;
-}
-
-int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)
-{
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	/* This is special hardware. We expect bus 0 and CS line 0 here. */
-	if ((bus != 0) || (cs != 0))
+	if ((dev->bus != 0) && (dev->cs != 0)) {
+		printk(BIOS_ERR, "%s: Unsupported device "
+		       "bus=0x%x,cs=0x%x!\n", __func__, dev->bus, dev->cs);
 		return -1;
+	}
 
-	slave->bus = bus;
-	slave->cs = cs;
-	slave->ctrlr = NULL;
-
-	return 0;
-}
-
-int spi_read_status(uint8_t *status)
-{
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	if (exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0,
-				 sizeof(*status)) != SUCCESS)
-		return -1;
-
-	drain_xfer_fifo(ctx, status, sizeof(*status));
-
+	printk(BIOS_INFO, "%s: Found controller for device "
+	       "(bus=0x%x,cs=0x%x)!!\n", __func__, dev->bus, dev->cs);
 	return 0;
 }
 
-int spi_flash_get_fpr_info(struct fpr_info *info)
-{
-	BOILERPLATE_CREATE_CTX(ctx);
-
-	if (!ctx->mmio_base)
-		return -1;
+static const struct spi_ctrlr fast_spi_ctrlr = {
+	.setup = fast_spi_ctrlr_setup,
+};
 
-	info->base = ctx->mmio_base + SPIBAR_FPR_BASE;
-	info->max = SPIBAR_FPR_MAX;
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+	{ .ctrlr = &fast_spi_ctrlr, .bus_start = 0, .bus_end = 0 },
+};
 
-	return 0;
-}
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);