diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-16 10:37:15 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-28 22:48:00 +0000 |
| commit | 81100bf7ff62c4ee53214afb82f2fa9112d109b6 (patch) | |
| tree | 8fdb92df42e60e200095aac64eb6b9781c54594f /src/soc/intel/apollolake | |
| parent | 4007d7f8c73d2872c6fe74f2b58a673161d6c947 (diff) | |
soc/intel: Move fill_postcar_frame to memmap.c
Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/memmap.c | 30 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 29 |
2 files changed, 30 insertions, 29 deletions
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 8b51a85b76..bda43bbdbf 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -15,9 +15,11 @@ * GNU General Public License for more details. */ +#include <arch/romstage.h> #include <assert.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/pci.h> #include <soc/systemagent.h> @@ -47,3 +49,31 @@ void smm_region(uintptr_t *start, size_t *size) *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t smm_base; + size_t smm_size; + + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + /* cbmem_top() needs to be at least 16 MiB aligned */ + assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); + postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, + MTRR_TYPE_WRBACK); + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 7e369f46c8..29498656dc 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -24,7 +24,6 @@ #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/pae.h> #include <delay.h> #include <cpu/x86/smm.h> @@ -221,34 +220,6 @@ void mainboard_romstage_entry(void) mainboard_save_dimm_info(); } -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - /* cbmem_top() needs to be at least 16 MiB aligned */ - assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); - postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, - MTRR_TYPE_WRBACK); - - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); -} - static void fill_console_params(FSPM_UPD *mupd) { if (CONFIG(CONSOLE_SERIAL)) { |