diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-06-22 18:58:14 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-24 20:32:19 +0200 |
| commit | 33fd66b46309b140ed9b228083a55a394117afea (patch) | |
| tree | 6584a3b887dfcc29235c264960b7a9c1d0c97105 /src/soc/intel/apollolake/romstage.c | |
| parent | 0f593c22a8a88068ffdf73f87ee9ce98c343a977 (diff) | |
soc/intel/apollolake: Move PMC BAR setup to bootblock
Some features of PMC needs to be accessed before romstage. Hence,
move PMC BARs setup into bootblock.
BUG=chrome-os-partner:54149
BRANCH=none
TEST=none
Change-Id: I14493498314ef1a4ce383e192edccf65fed2d2cb
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15332
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/romstage.c')
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 0c8f1c2de7..ce28326392 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -65,28 +65,14 @@ static struct chipset_power_state power_state CAR_GLOBAL; /* * Enables several BARs and devices which are needed for memory init * - MCH_BASE_ADDR is needed in order to talk to the memory controller - * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded) - * Once raminit is done, we can safely let the allocator re-assign them * - HPET is enabled because FSP wants to store a pointer to global data in the * HPET comparator register */ static void soc_early_romstage_init(void) { - device_t pmc = PMC_DEV; - /* Set MCH base address and enable bit */ pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1); - /* Set PMC base addresses and enable decoding. */ - pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); - pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ - pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); - pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ - pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); - pci_write_config16(pmc, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); - /* Enable decoding for HPET. Needed for FSP global pointer storage */ pci_write_config8(P2SB_DEV, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | P2SB_HPTC_ADDRESS_ENABLE); |