diff options
| author | Lance Zhao <lijian.zhao@intel.com> | 2016-04-19 18:04:21 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-04-28 05:47:30 +0200 |
| commit | 1bd0c0c4971ce50426cbe18e93e2ec9dca320af1 (patch) | |
| tree | ede27d29edc980ed7cd8ca393f8716b50dc52ee4 /src/soc/intel/apollolake/lpc.c | |
| parent | 164e8f1d9b9a36ccca2feefa0e2172ac0c3254c3 (diff) | |
soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds
Add chromeos required GNVS feature. The GNVS table stays in both CBMEM
and ACPI DSDT tables.
Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14471
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/lpc.c')
| -rw-r--r-- | src/soc/intel/apollolake/lpc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 6e366e095f..06ca0db7b1 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -86,6 +86,7 @@ static struct device_operations device_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = &lpc_init }; |