From 1bd0c0c4971ce50426cbe18e93e2ec9dca320af1 Mon Sep 17 00:00:00 2001 From: Lance Zhao Date: Tue, 19 Apr 2016 18:04:21 -0700 Subject: soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/lpc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/apollolake/lpc.c') diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 6e366e095f..06ca0db7b1 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -86,6 +86,7 @@ static struct device_operations device_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = &lpc_init }; -- cgit v1.2.3