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authorAndrey Petrov <andrey.petrov@intel.com>2016-07-14 17:16:35 -0700
committerAaron Durbin <adurbin@chromium.org>2016-07-19 20:19:51 +0200
commitfcd51ffae86752f2794e1e5998b84f7119b7f091 (patch)
treec7e90d325d36b276c95be4c8407b9fb339f1d354 /src/soc/intel/apollolake/include
parent35d42c75648dee229dbf0a8adc0ebfa2ddf81dd4 (diff)
soc/intel/apollolake: Add basic HECI support
Add functions to read Host Firmware Status register and a helper function to determine if CSE is ready. BUG=chrome-os-partner:55055 TEST=none Change-Id: If511a51c04f7e59427d7952fa67b61060e2be404 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15713 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
-rw-r--r--src/soc/intel/apollolake/include/soc/heci.h43
-rw-r--r--src/soc/intel/apollolake/include/soc/pci_devs.h3
2 files changed, 46 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/heci.h b/src/soc/intel/apollolake/include/soc/heci.h
new file mode 100644
index 0000000000..1151321445
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/heci.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_APOLLOLAKE_HECI_H_
+#define _SOC_APOLLOLAKE_HECI_H_
+
+enum sec_status {
+ SEC_STATE_RESET = 0,
+ SEC_STATE_INIT,
+ SEC_STATE_RECOVERY,
+ SEC_STATE_UNKNOWN0,
+ SEC_STATE_UNKNOWN1,
+ SEC_STATE_NORMAL,
+ SEC_STATE_DISABLE_WAIT,
+ SEC_STATE_TRANSITION,
+ SEC_STATE_INVALID_CPU
+};
+
+#define REG_SEC_FW_STS0 0x40
+#define MASK_SEC_FIRMWARE_COMPLETE (1 << 9)
+#define MASK_SEC_STATUS 0xf
+
+/* Read Firmware Status register */
+uint32_t heci_fw_sts(void);
+/* Returns true if CSE is in normal status */
+bool heci_cse_normal(void);
+/* Returns true if CSE is done with whatever it was doing */
+bool heci_cse_done(void);
+
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index f29784d974..b7519ed799 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -46,6 +46,9 @@
#define HDA_DEV _PCI_DEV(0xe, 0)
#define HDA_DEVFN _PCI_DEVFN(0xe, 0)
+#define CSE_DEV _PCI_DEV(0xf, 0)
+#define CSE_DEVFN _PCI_DEVFN(0xf, 0)
+
#define ISH_DEV _PCI_DEV(0x11, 0)
#define ISH_DEVFN _PCI_DEVFN(0x11, 0)