diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-10-10 12:34:28 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-14 18:10:05 +0100 |
| commit | a012254d010d9d06f8dea1c4b6cc27b57b39007f (patch) | |
| tree | dc6e56d21ab9f3a3a40570295c675442aa8e0a7d /src/soc/intel/apollolake/include | |
| parent | a09b338362c09aebf5f35a63b2412f358621db0f (diff) | |
intel/apollolake: Enable turbo
This patch adds punit initialization code after
FspMemoryInit so that turbo can be initialized after
that.
BUG=chrome-os-partner:58158
BRANCH=None
Change-Id: I4939da47da82b9a728cf1b5cf6d5ec54b4f5b31d
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/17203
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/cpu.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/iomap.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pci_devs.h | 3 |
3 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index e94972d90b..66fc29babc 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -23,6 +23,7 @@ #include <device/device.h> void apollolake_init_cpus(struct device *dev); +void set_max_freq(void); #endif #define CPUID_APOLLOLAKE_A0 0x506c8 @@ -88,4 +89,7 @@ void apollolake_init_cpus(struct device *dev); /* Common Timer Copy (CTC) frequency - 19.2MHz. */ #define CTC_FREQ 19200000 +/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */ +#define APL_BURST_MODE_DISABLE 0x40 + #endif /* _SOC_APOLLOLAKE_CPU_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index d5d8f878ef..3c94d1b608 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,6 +25,12 @@ #define MCH_BASE_ADDR 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) +#define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR 0x7168 +#define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR 0x7078 +#define PUNIT_THERMAL_DEVICE_IRQ 0x700C +#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18 +#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 + #define ACPI_PMIO_BASE 0x400 #define ACPI_PMIO_SIZE 0x100 #define R_ACPI_PM1_TMR 0x8 diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 0d9e28847c..d058f8b946 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -34,6 +34,9 @@ #define NB_DEVFN _PCI_DEVFN(0, 0) #define NB_DEV_ROOT _PCI_DEV(0x0, 0) +#define PUNIT_DEV _PCI_DEV(0, 1) +#define PUNIT_DEVFN _PCI_DEVFN(0x0, 1) + #define IGD_DEV _PCI_DEV(0x2, 0) #define IGD_DEVFN _PCI_DEVFN(0x2, 0) |