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authorSubrata Banik <subrata.banik@intel.com>2017-03-10 13:51:11 +0530
committerAaron Durbin <adurbin@chromium.org>2017-03-22 04:55:13 +0100
commit8e1c12f12e3fb01d2228cca29de188507b3f2cc7 (patch)
tree1ec7269b2b8d053e250d85b78bbe01bf74d2bdea /src/soc/intel/apollolake/include
parentf0637e71c78f9c16749e3d1a97988bde3523454e (diff)
soc/intel/apollolake: Add CQOS config for CAR common code
Change-Id: I5947170a96e888cea2f3faac92355e72b63c1fef Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
-rw-r--r--src/soc/intel/apollolake/include/soc/cpu.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index b4c86842ba..f2722d6d39 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -83,12 +83,6 @@ void enable_untrusted_mode(void);
#define CACHE_BITS_PER_MASK 8
#define CACHE_LINE_SIZE 64
#define CACHE_SETS 1024
-/*
- * Each bit in QOS mask controls this many bytes. This is calculated as:
- * (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
- */
-#define CACHE_QOS_SIZE_PER_BIT (128 * KiB)
-#define L2_CACHE_SIZE 0x100000
#define BASE_CLOCK_MHZ 100