lpss_i2c: Set SDA hold and support custom speed config

This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.

For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific.  The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.

Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.

And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.

Since these custom speed configs will come from devicetree a macro is
added to simplify the description:

register "i2c[4].speed_config" = "{
	 LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
	 LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
	 LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
	 LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"

Which will result in the following speed config in \_SB.PCI0.I2C4:

Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })

Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

0 files changed, 0 insertions, 0 deletions