soc/intel/common/block: Move tco common functions into block/smbus

This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc
code into common/block/smbus.

BUG=b:78109109
BRANCH=NONE
TEST=Build and boot KBL/CNL/APL/ICL platform.

Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/26166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

4 files changed, 34 insertions, 5 deletions

diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index b1cf3da88a..8e2986d8b7 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -29,6 +29,9 @@
 #define ACPI_BASE_SIZE			0x100
 #define R_ACPI_PM1_TMR			0x8
 
+#define TCO_BASE_ADDRESS	(ACPI_BASE_ADDRESS + 0x60)
+#define TCO_BASE_SIZE		0x20
+
 /* CST Range (R/W) IO port block size */
 #define PMG_IO_BASE_CST_RNG_BLK_SIZE	0x5
 /* ACPI PMIO Offset to C-state register*/
diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h
index 4af8f2c23e..264704c755 100644
--- a/src/soc/intel/apollolake/include/soc/pcr_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h
@@ -40,5 +40,6 @@
 #define PID_TUNIT	0x52
 
 #define PID_PSF3	0xC6
+#define PID_DMI	0x00 /* Reserved */
 
 #endif	/* SOC_INTEL_APL_PCR_H */
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index c4f1d1b39c..61c97cebb5 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -131,10 +131,6 @@
 
 #define GPE_CNTL		0x50
 #define DEVACT_STS		0x4c
-#define TCO_STS			0x64
-#define   TCO_TIMEOUT		(1 << 3)
-#define TCO1_CNT		0x68
-#define   TCO_TMR_HLT		(1 << 11)
 
 #define GPE0_REG_MAX		4
 #define GPE0_REG_SIZE		32
@@ -240,7 +236,8 @@ struct chipset_power_state {
 	uint32_t pm1_cnt;
 	uint32_t gpe0_sts[GPE0_REG_MAX];
 	uint32_t gpe0_en[GPE0_REG_MAX];
-	uint32_t tco_sts;
+	uint16_t tco1_sts;
+	uint16_t tco2_sts;
 	uint32_t prsts;
 	uint32_t gen_pmcon1;
 	uint32_t gen_pmcon2;
diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h
new file mode 100644
index 0000000000..4b252d61a9
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/smbus.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_APOLLOLAKE_SMBUS_H_
+#define _SOC_APOLLOLAKE_SMBUS_H_
+
+/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
+#define TCO1_STS			0x04
+#define  TCO_TIMEOUT			(1 << 3)
+#define TCO2_STS			0x06
+#define  TCO_STS_SECOND_TO		(1 << 1)
+#define TCO1_CNT			0x08
+#define  TCO_LOCK			(1 << 12)
+#define  TCO_TMR_HLT			(1 << 11)
+
+#endif