diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2018-02-27 13:23:42 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-03-20 02:04:06 +0000 |
| commit | 3669a06c95aac12bde82bab8300dfdd11cc3e142 (patch) | |
| tree | 086850a2aa55da50976a8b9defbd0c218ab3b071 /src/soc/intel/apollolake/include | |
| parent | f46bd356637c7280b104c3d55405c650e6e65633 (diff) | |
soc/intel/apollolake: Add support for GSPI
BUG=b:73133848
BRANCH=None
TEST=Build coreboot for Octopus board. Tested the GSPI interface
with a SPI EEPROM and got correct response to a RDID command
Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/24906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/iomap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index d4cd0952e8..7e6a795c58 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -48,6 +48,7 @@ /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 +#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 /* Temporary BAR for early I2C bus access */ #define PRERAM_I2C_BASE_ADDRESS(x) (0xfe020000 + (0x1000 * (x))) |