From 3669a06c95aac12bde82bab8300dfdd11cc3e142 Mon Sep 17 00:00:00 2001 From: Ravi Sarawadi Date: Tue, 27 Feb 2018 13:23:42 -0800 Subject: soc/intel/apollolake: Add support for GSPI BUG=b:73133848 BRANCH=None TEST=Build coreboot for Octopus board. Tested the GSPI interface with a SPI EEPROM and got correct response to a RDID command Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Signed-off-by: Ravi Sarawadi Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/24906 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/include/soc/iomap.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index d4cd0952e8..7e6a795c58 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -48,6 +48,7 @@ /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 +#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 /* Temporary BAR for early I2C bus access */ #define PRERAM_I2C_BASE_ADDRESS(x) (0xfe020000 + (0x1000 * (x))) -- cgit v1.2.3