diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-07-19 13:50:09 +0100 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-17 19:48:41 +0000 |
| commit | 03f6820194218ce32cc5497eec0c02c74b67bf6e (patch) | |
| tree | c8ae2e99c8d7de7cbb540d36f19ef6ddd0d89ab4 /src/soc/intel/apollolake/cse.c | |
| parent | b660f4ee47ac2eab478a541af5f0e9217236ae22 (diff) | |
soc/intel/apollolake: Add the remaining CSE Firmware Status Registers
Add the Shadow Registers from 2 through 5 and print information
from them accordingly. All values were taken from Intel document
number 571993.
Tested on the StarLite Mk III and the correct values are
shown:
[DEBUG] CSE: IBB Verification Result: PASS
[DEBUG] CSE: IBB Verification Done : YES
[DEBUG] CSE: Actual IBB Size : 88
[DEBUG] CSE: Verified Boot Valid : FAIL
[DEBUG] CSE: Verified Boot Test : NO
[DEBUG] CSE: FPF status : FUSED
Please note, the values shown are in an error state.
This replaces the Fuse check that is done via Heci, as this will only
work whilst the CSE is in a normal state.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8a9e7b329010fae1a2ed9c3fefc9765e617cdfe4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/apollolake/cse.c')
| -rw-r--r-- | src/soc/intel/apollolake/cse.c | 43 |
1 files changed, 24 insertions, 19 deletions
diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 8473d20aef..01c4c474c2 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -158,16 +158,21 @@ static uint32_t dump_status(int index, int reg_addr) static void dump_cse_state(void) { union cse_fwsts1 fwsts1; + union cse_fwsts2 fwsts2; + union cse_fwsts3 fwsts3; + union cse_fwsts4 fwsts4; + union cse_fwsts5 fwsts5; + union cse_fwsts6 fwsts6; if (!is_cse_enabled()) return; fwsts1.data = dump_status(1, PCI_ME_HFSTS1); - dump_status(2, PCI_ME_HFSTS2); - dump_status(3, PCI_ME_HFSTS3); - dump_status(4, PCI_ME_HFSTS4); - dump_status(5, PCI_ME_HFSTS5); - dump_status(6, PCI_ME_HFSTS6); + fwsts2.data = dump_status(2, PCI_ME_HFSTS2); + fwsts3.data = dump_status(3, PCI_ME_HFSTS3); + fwsts4.data = dump_status(4, PCI_ME_HFSTS4); + fwsts5.data = dump_status(5, PCI_ME_HFSTS5); + fwsts6.data = dump_status(6, PCI_ME_HFSTS6); printk(BIOS_DEBUG, "CSE: Working State : %u\n", fwsts1.fields.working_state); @@ -181,20 +186,20 @@ static void dump_cse_state(void) fwsts1.fields.error_code); printk(BIOS_DEBUG, "CSE: Operation Mode : %u\n", fwsts1.fields.operation_mode); - - printk(BIOS_DEBUG, "CSE: FPF status : "); - switch (g_fuse_state) { - case FUSE_FLASH_UNFUSED: - printk(BIOS_DEBUG, "unfused"); - break; - case FUSE_FLASH_FUSED: - printk(BIOS_DEBUG, "fused"); - break; - default: - case FUSE_FLASH_UNKNOWN: - printk(BIOS_DEBUG, "unknown"); - } - printk(BIOS_DEBUG, "\n"); + printk(BIOS_DEBUG, "CSE: IBB Verification Result: %s\n", + fwsts3.fields.ibb_verif_result ? "PASS" : "FAIL"); + printk(BIOS_DEBUG, "CSE: IBB Verification Done : %s\n", + fwsts3.fields.ibb_verif_done ? "YES" : "NO"); + printk(BIOS_DEBUG, "CSE: Actual IBB Size : %u\n", + fwsts3.fields.ibb_size); + printk(BIOS_DEBUG, "CSE: Verified Boot Valid : %s\n", + fwsts4.fields.txe_veri_boot_valid ? "PASS" : "FAIL"); + printk(BIOS_DEBUG, "CSE: Verified Boot Test : %s\n", + fwsts4.fields.txe_veri_boot_test ? "YES" : "NO"); + printk(BIOS_DEBUG, "CSE: FPF status : %s\n", + fwsts6.fields.fpf_commited ? "FUSED" : "UNFUSED"); + printk(BIOS_DEBUG, "CSE: Error Status Code : %u\n", + fwsts5.fields.error_status_code); } #define PCR_PSFX_T0_SHDW_PCIEN 0x1C |