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authorJulius Werner <jwerner@chromium.org>2022-11-23 18:20:32 -0800
committerYu-Ping Wu <yupingso@google.com>2022-12-07 02:38:40 +0000
commit4924e422750474482087b202724f9cfa32de047d (patch)
tree4acc0a4a06727fb136e5faa24f2285a6ab4db6bc /src/soc/intel/apollolake/chipset_apl.cb
parentd5c5b5233d0ee35b02eefc5f1db33ff92f878161 (diff)
build: Combine "savedefconfig" and "stripped config" in CBFS `config`
The intention of CB:69710 was that the expanded config file introduced there would be a strict superset of the old version and could be used in all the same cases. This is generally true except for a small oversight: if a boolean Kconfig is `default y`, but was manually set to `n` by the user, the new `config` file does not include a line for it. Running `make olddefconfig` on such a file will again introduce the option as `y`. It turns out that `make olddefconfig` actually parses those "load-bearing comments" in that case. This patch fixes the problem by also generating the minimal defconfig (like before CB:69710), and then just appending the non-comment lines from the full config that don't appear in it already. This ensures that any "load-bearing comments" in the defconfig remain in the file and the result of Kconfig utilities regenerating a full config from there will again be the same as before CB:69710. In addition, it clearly separates the "minimal defconfig" part of the file from the rest, making it easy for people to extract that if they need it; while also keeping all the config values in one file to make it easy to grep for a certain value. Also eliminate that random backslash in the recipe that doesn't seem to have any good reason to exist and was probably a typo to begin with. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I52ba5d20d3536498fae79d529acf7135f97ef1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/chipset_apl.cb')
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