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authorSumeet R Pawnikar <sumeet.r.pawnikar@intel.com>2020-05-09 15:37:09 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:09:09 +0000
commit2adb50d32e8cd9c61773b1d60de545255c6a4049 (patch)
tree0c78815666d0b53bf54130e9752690ba29e61c08 /src/soc/intel/apollolake/chip.h
parenta54bfd5e950ef108e9941a8319d0c24d786528ec (diff)
apollolake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Apollo Lake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on octopus system Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.h')
-rw-r--r--src/soc/intel/apollolake/chip.h9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 8c0a6d2d1a..ce446a063a 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -9,6 +9,7 @@
#include <soc/gpe.h>
#include <soc/gpio.h>
#include <intelblocks/lpc_lib.h>
+#include <intelblocks/power_limit.h>
#include <device/i2c_simple.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <soc/pm.h>
@@ -28,6 +29,9 @@ struct soc_intel_apollolake_config {
/* Common structure containing soc config data required by common code*/
struct soc_intel_common_config common_soc_config;
+ /* Common struct containing power limits configuration info */
+ struct soc_power_limits_config power_limits_config;
+
/*
* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
* four CLKREQ inputs, but six root ports. Root ports without an
@@ -99,11 +103,6 @@ struct soc_intel_apollolake_config {
/* TCC activation offset value in degrees Celsius */
int tcc_offset;
- /* PL1 override value in mW for APL */
- uint16_t tdp_pl1_override_mw;
- /* PL2 override value in mW for APL */
- uint16_t tdp_pl2_override_mw;
-
/* Configure Audio clk gate and power gate
* IOSF-SB port ID 92 offset 0x530 [5] and [3]
*/