From 2adb50d32e8cd9c61773b1d60de545255c6a4049 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Sat, 9 May 2020 15:37:09 +0530 Subject: apollolake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Apollo Lake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on octopus system Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/chip.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'src/soc/intel/apollolake/chip.h') diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 8c0a6d2d1a..ce446a063a 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,9 @@ struct soc_intel_apollolake_config { /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Common struct containing power limits configuration info */ + struct soc_power_limits_config power_limits_config; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an @@ -99,11 +103,6 @@ struct soc_intel_apollolake_config { /* TCC activation offset value in degrees Celsius */ int tcc_offset; - /* PL1 override value in mW for APL */ - uint16_t tdp_pl1_override_mw; - /* PL2 override value in mW for APL */ - uint16_t tdp_pl2_override_mw; - /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] */ -- cgit v1.2.3