diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-05-22 14:44:27 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-01 15:41:22 +0000 |
| commit | f165bbdcf043dd9753c3b3a8e4ae86b0bfcd78ee (patch) | |
| tree | f99bbe11deb064a409ae7e74398a3248827c1be6 /src/soc/intel/apollolake/chip.c | |
| parent | 385f4bb965cd0f67958d77389d5185a38cb3c9d8 (diff) | |
soc/intel/apollolake: Make SATA speed limit configurable
In cases where there are limitations on the mainboard it can be
necessary to limit the used SATA speed even though both, the SATA
controller and disk drive support a higher speed rate. The FSP parameter
'SpeedLimit' allows to set the speed limit.
It should be noted that Gen 3 equals the default value '0'. This means
that inside FSP the same code is executed.
This patch provides a chip config so that this FSP parameter can be
set as needed in the devicetree on mainboard level.
Change-Id: I9c3eda0649546e3a40eb24a015b7c6efd8f90e0f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75364
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index e7a8168c94..bd40595ea3 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -736,6 +736,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* SATA config */ if (is_devfn_enabled(PCH_DEVFN_SATA)) { silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport); + silconfig->SpeedLimit = cfg->sata_speed; memcpy(silconfig->SataPortsEnable, cfg->SataPortsEnable, sizeof(silconfig->SataPortsEnable)); } |